mgpu-arch, Qgpu-arch

Builds the offload code for graphics to run on a particular version of the processor graphics, as specified by the option value. It causes the linker to invoke a compiler that translates the virtual Instruction Set Architecture (ISA) of the offload executable into the native ISA for the version of the processor graphics specified. This option only applies to Intel® Graphics Technology.

Architecture Restrictions

Only available on IA-32 architecture targeting Intel® Graphics Technology, and on Intel® 64 architecture targeting Intel® Graphics Technology

Syntax

Linux:

-mgpu-arch=arch

OS X:

None

Windows:

/Qgpu-arch:arch

Arguments

arch

Indicates to the compiler the target ISA for the compilation. Possible values are:

broadwell	May generate instructions for the graphics processor that is on Intel® microarchitecture code name Broadwell.
haswell	May generate instructions for the graphics processor that is on Intel® microarchitecture code name Haswell.
ivybridge (deprecated)	May generate instructions for the graphics processor that is on Intel® microarchitecture code name Ivy Bridge.

Default

OFF	The compiler generates virtual ISA instructions. At runtime, the virtual instructions must be compiled into native ISA code for the platform on which the executable is to run.

Description

This option builds the offload code for graphics to runon a particular version of the processor graphics, as specified by the option value. It causes the linker to invoke a compiler that translates the virtual Instruction Set Architecture (ISA) of the offload executable into the native ISA for the version of the processor graphics specified. For information about applicable operating systems for Intel® Graphics Technology, see Overview: Intel® Graphics Technology.

When this option is not used, the executable is based on the virtual ISA, which is portable across platforms. In this case, the virtual ISA is compiled at runtime by invoking the "Just-In-Time" compiler.

This option should improve performance of native code generation for graphics applications because the compilation will be performed at link time instead of at runtime. It may also help you avoid some overhead costs associated with compiling virtual ISA code at runtime.

The following shows the current mapping table for the possible ISA target values:

ISA target value	Intel® Core™ processors	Pentium® Processors	Celeron® Processor
broadwell	5th Generation Intel® Core™ Processors	Processor Model Numbers: 3xxx[Y or M]	Processor Model Numbers: 3xxx or 2xxx[Y or M]
haswell	4th Generation Intel® Core™ Processors	Processor Model Numbers: 3xx	Processor Model Numbers: 29xx
ivybridge (deprecated)	3rd Generation Intel® Core™ Processors	Processor Model Numbers: 20xx	Processor Model Numbers: 10xx

IDE Equivalent

None

Alternate Options

None