Intel® C++ Compiler 16.0 User and Reference Guide
Fixes up NaNs from float64 vectors. Corresponding instruction is VFIXUPNANPD. This intrinsic only applies to Intel® Many Integrated Core Architecture (Intel® MIC Architecture).
Without Mask extern __m512d __cdecl _mm512_fixupnan_pd(__m512d v1, __m512d v2, __m512i v3); |
With Mask extern __m512d __cdecl _mm512_mask_fixupnan_pd(__m512d v1, __mmask8 k1, __m512d v2, __m512i v3); |
v1 |
float64 vector used for the operation |
v2 |
float64 vector used for the operation |
v3 |
int32 vector used for the operation |
v1_old |
Source vector that retains old values of the destination vector; the resulting vector gets corresponding elements from v1_old for zero mask bits |
k1 |
Writemask; only those elements of the source vectors with corresponding bit set to '1' in the k1 mask are computed and stored in the result; elements in the result vector corresponding to zero bit in k1 are copied from corresponding elements of vector v1_old |
Fixes up NaNs from float64 vectors v1 and v2, returning the quietized NaN from v1 as v3.
The masked variant has one additional argument: k1. Only those elements in the source registers with the corresponding bit set in vector mask k1 are used for computing.
Returns the result of the operation.