Intel® C++ Compiler 16.0 User and Reference Guide
This topic only applies to Intel® Many Integrated Core Architecture (Intel® MIC Architecture).
The heterogeneous compilation environment consists of a host CPU compilation environment and a target compilation environment. Each environment consists of the compiler, linker and standard libraries. Code for the host CPU is compiled within the host environment and offloaded code within the target environment. The target environment may supply its own sets of standard libraries and these would be available to be called from offloaded code with no need to use special syntax or runtime features.
Some common libraries, such as the Intel® Math Kernel Library (Intel® MKL) and Intel® Performance Primitives (Intel® IPP) will be available in CPU versions as well as target versions.
When the target is available, the target executable is loaded when the CPU version of the executable is loaded, or when the first offload is attempted. At this time the libraries linked with the target code are initialized. The loaded target executable remains in the target memory until the host program terminates. Thus, any global state maintained by the library is maintained across offload instances.
When you offload code only within shared libraries, you must link the main program with the [Q]offload compiler option.
Separate copies of libraries are linked or loaded with the host program and the offloaded target code. So there are two sets of global state: One on the host CPU and one on the target. The host CPU code only sees the host CPU state and the offloaded code only sees the state of the library on the target.
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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |