Intel® C++ Compiler 16.0 User and Reference Guide

_mm512_reduce_[g]min_pd/_mm512_mask_reduce_[g]min_pd

Determines the element with minimum scalar value in a float64 vector. There is no corresponding instruction. This intrinsic only applies to Intel® Many Integrated Core Architecture (Intel® MIC Architecture).

Syntax

Without mask

extern double __cdecl _mm512_reduce_gmin_pd(_m512d v2);

extern double __cdecl _mm512_reduce_min_pd(_m512d v2);

Withmask

extern double __cdecl _mm512_mask_reduce_gmin_pd(__mmask8 k1, _m512d v2);

extern double __cdecl _mm512_mask_reduce_min_pd(__mmask8 k1, _m512d v2);

Parameters

v2

float64 vector in which to determine the minimum value

k1

Writemask; only those elements of the source vectors with corresponding bit set to '1' in the k1 mask are computed and stored in the result

Description

Determines the element with minimum value in the float64 vector v2.

The masked variant has one additional argument: k1. Only those elements in the source registers with the corresponding bit set in vector mask k1 are used for computing. Elements in v2 with corresponding bit clear in k1 are copied as is to the resulting vector.

For the g variant:

FpMin() returns the smaller of the two elements in v2, following IEEE in general, and specifically following this from the DX10 spec:

dest = src0 < src1 ? src0 : src1

 NaN has special handling: If one element is NaN, then the other element is returned (choice made per-component). If both are NaN, then the quietized NaN from the first element in v2 is returned. This conforms to new IEEE 754R rules.

For the non-g variant:

FpMin() returns the smaller of the two elements in v2 by performing a SIMD compare of the packed single-precision floating-point values in those two elements .

If the values being compared are both 0.0s (of either sign), the value in the second element in v1 is returned. If only one value is a NaN, the second element in v2, either a NaN or a valid floating-point value, is written to the result.

Returns

Returns the result of the operation.