Intel® C++ Compiler 16.0 User and Reference Guide
Provides the ability to declare that a version of a function is targeted at particular type(s) of processors.
Windows* OS: __declspec(cpu_specific(cpuid)) |
Linux* OS: __attribute__((cpu_specific(cpuid))) |
cpuid |
Possible values are: atom: Intel® Atom™ processors with Intel® Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3) atom_sse4_2: Intel® Atom™ processors with Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) atom_sse4_2_movbe: Intel® Atom™ processors with Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) with MOVBE instructions enabled core_2_duo_sse4_1: Intel® 45nm Hi-k next generation Intel® Core™ microarchitecture processors with Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1) instructions core_2_duo_ssse3: Intel® Core™2 Duo processors and Intel® Xeon® processors with Intel® Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3) instructions core_2nd_gen_avx: 2nd generation Intel® Core™ processor family with support for Intel® Advanced Vector Extensions (Intel® AVX) core_3rd_gen_avx: 3rd generation Intel® Core™ processor family with support for Intel® Advanced Vector Extensions (Intel® AVX) including the RDRND instruction core_4th_gen_avx: 4th generation Intel® Core™ processor family with support for Intel® Advanced Vector Extensions 2 (Intel® AVX2) including the RDRND instruction core_4th_gen_avx_tsx: 4th generation Intel® Core™ processor family with support for Intel® Advanced Vector Extensions 2 (Intel® AVX2) including the RDRND instruction, and support for Intel® Transactional Synchronization Extensions (Intel® TSX) core_5th_gen_avx: 5th generation Intel® Core™ processor family with support for Intel® Advanced Vector Extensions 2 (Intel® AVX2) including the RDSEED and Multi-Precision Add-Carry Instruction Extensions (ADX) instructions core_5th_gen_avx_tsx: 5th generation Intel® Core™ processor family with support for Intel® Advanced Vector Extensions 2 (Intel® AVX2) including the RDSEED and Multi-Precision Add-Carry Instruction Extensions (ADX) instructions, and support for Intel® Transactional Synchronization Extensions (Intel® TSX) core_aes_pclmulqdq: Intel® Core™ processors with support for Advanced Encryption Standard (AES) instructions and carry-less multiplication instruction core_i7_sse4_2: Intel® Core™ i7 processors with Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) instructions generic: Other Intel processors for IA-32 or Intel® 64 architecture or compatible processors not provided by Intel Corporation mic: Intel® Many Integrated Core Architecture (Intel® MIC Architecture) mic_avx512: 2nd generation Intel® Xeon Phi™ processor family with support for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection instructions, Intel® AVX-512 Exponential and Reciprocal instructions, Intel® AVX-512 Prefetch instructions for Intel® processors, and Intel® Advanced Vector Extensions 2 (Intel® AVX2) including the RDSEED and Multi-Precision Add-Carry Instruction Extensions (ADX) instructions. This setting is only available on Intel® 64 architecture targeting the Intel® Xeon Phi™ coprocessor (code name Knights Landing). pentium: Intel® Pentium® processor pentium_4: Intel® Pentium® 4 processors pentium_4_sse3: Intel® Pentium® 4 processor with Intel® Streaming SIMD Extensions 3 (Intel® SSE3) instructions, Intel® Core™ Duo processors, Intel® Core™ Solo processors pentium_ii: Intel® Pentium® II processors pentium_iii: Intel® Pentium® III processors pentium_iii_no_xmm_regs: Intel® Pentium® III processors with no XMM registers pentium_m: Intel® Pentium® M processors pentium_mmx: Intel® Pentium® processors with MMX™ technology pentium_pro: Intel® Pentium® Pro processors
|
Use this keyword to declare each function version targeted at particular type(s) of processors.
This feature is available only for Intel processors based on IA-32 or Intel® 64 architecture. It is not available for non-Intel processors. Applications built using the manual processor dispatch feature may be more highly optimized for Intel processors than for non-Intel processors.
|
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |