qopt-mem-layout-trans, Qopt-mem-layout-trans

Controls the level of memory layout transformations performed by the compiler. Option -qopt-mem-layout-trans is the replacement option for -opt-mem-layout-trans, which is deprecated.

Architecture Restrictions

Not available on Intel® 64 architecture targeting the Intel® Xeon Phi™ coprocessor x100 product family (formerly code name Knights Corner)

Syntax

Linux and OS X:

-qopt-mem-layout-trans[=n]

-qno-opt-mem-layout-trans

Windows:

/Qopt-mem-layout-trans[:n]

/Qopt-mem-layout-trans-

Arguments

n

Is the level of memory layout transformations. Possible values are:

0	Disables memory layout transformations. This is the same as specifying -qno-opt-mem-layout-trans (Linux* and OS X) or /Qopt-mem-layout-trans- (Windows).
1	Enables basic memory layout transformations.
2	Enables more memory layout transformations. This is the same as specifying [q or Q]opt-mem-layout-trans with no argument.
3	Enables aggressive memory layout transformations. You should only use this setting if your system has more than 4GB of physical memory per core.

Default

-qopt-mem-layout-trans=2 or /Qopt-mem-layout-trans:2

The compiler performs moderate memory layout transformations.

Description

This option controls the level of memory layout transformations performed by the compiler. This option can improve cache reuse and cache locality.

Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

IDE Equivalent

None

Alternate Options

None