arch

Architecture Restrictions

Not available on Intel® 64 architecture targeting the Intel® Xeon Phi™ coprocessor x100 product family (formerly code name Knights Corner)

Syntax

Linux and OS X:

-arch code

Windows:

/arch:code

Arguments

code

Indicates to the compiler a feature set that it may target, including which instruction sets it may generate. Many of the following descriptions refer to Intel® Streaming SIMD Extensions (Intel® SSE) and Supplemental Streaming SIMD Extensions (SSSE). Possible values are:

CORE-AVX2	May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.
CORE-AVX-I	May generate the RDRND instruction, Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.
AVX	May generate Intel® Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.
SSE4.2	May generate Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.
SSE4.1	May generate Intel® SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.
SSSE3	May generate SSSE3 instructions and Intel® SSE3, SSE2, and SSE instructions.
SSE3	May generate Intel® SSE3, SSE2, and SSE instructions.
SSE2	May generate Intel® SSE2 and SSE instructions. This value is only available on Linux* and Windows* systems.
SSE	This option has been deprecated; it is now the same as specifying IA32.
IA32	Generates x86/x87 generic code that is compatible with IA-32 architecture. Disables any default extended instruction settings, and any previously set extended instruction settings. It also disables all feature-specific optimizations and instructions. This value is only available on Linux* and Windows* systems using IA-32 architecture.

Default

Windows and Linux systems: SSE2
OS X systems using IA-32 architecture: SSE3
OS X systems using Intel® 64 architecture: SSSE3

For more information on the default values, see Arguments above.

Description

This option tells the compiler which features it may target, including which instruction sets it may generate.

Code generated with these options should execute on any compatible, non-Intel processor with support for the corresponding instruction set.

Options /arch and /Qx are mutually exclusive. If both are specified, the compiler uses the last one specified and generates a warning.

If you specify both the /Qax and /arch options, the compiler will not generate Intel-specific instructions.

For compatibility with Compaq* Visual Fortran, the compiler allows the following keyword values. However, you should use the suggested replacements.

Compatibility Value	Suggested Replacement
pn1	-mia32 or /arch:IA32
pn2	-mia32 or /arch:IA32
pn3	-mia32 or /arch:IA32
pn4	-msse2 or /arch:SSE2

IDE Equivalent

Visual Studio: Code Generation > Enable Enhanced Instruction Set

Eclipse: None

Xcode: None

Alternate Options

Linux and OS X: -m

Windows: None