Intel® Math Kernel Library 11.3 Update 4 Developer Guide
The most significant parameters in HPL.dat are N, NB, P and Q. Specify them as follows, as well as some other parameters:
P and Q - the number of rows and columns in the process grid, respectively.
P*Q must be the number of MPI processes that HPL is using.
For the hybrid offload version of the Intel Optimized MP LINPACK Benchmark, keep P and Q roughly the same size.
This setting is different from settings recommended for most HPL implementations, which usually recommend to choose P < Q and possibly with the 1:4 ratio.
NB - block size of the data distribution.
The table below shows recommended values of NB for 2nd and 3rd generation Intel® Core™ processors and for different numbers of Intel Xeon Phi coprocessors. The values may vary and depend on the PCI Express settings and performance of main memory.
No coprocessors |
1 coprocessor |
2 coprocessors |
3 coprocessors |
---|---|---|---|
256 |
960 |
1024 |
1200 |
N - the problem size:
For homogeneous runs, choose N divisible by NB*LCM(P,Q), where LCM is the least common multiple of the two numbers.
For heterogeneous runs, refer to Heterogeneous Intel Optimized MP LINPACK Benchmark.
Note that increasing N usually increases performance, but the size of N is bounded by memory.
Other parameters.
To use Intel MKL BPUSH algorithm for horizontal broadcast, in line 23 of HPL.dat, set the BCASTs parameter to 6.
Enabling NUMA on your system and running an MPI process for each NUMA socket usually improves the hybrid offload performance. Refer to your BIOS settings for enabling NUMA on your system. You can use HPL_MIC_DEVICE and HPL_MIC_SHAREMODE environment variables to share the Intel Xeon Phi coprocessors among MPI processes (see Environment Variables for the Hybrid Offload for details). The scripts runme_intel64 and runme_intel64_dynamic set these environment variables for you for a given number of MPI ranks per node.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |