Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help
In x86 architectures, mappings between virtual and physical memory are facilitated by a page table, which is kept in memory. To minimize references to this table, recently-used portions of the page table are cached in a hierarchy of 'translation look-aside buffers', or TLBs, which are consulted on every virtual address translation. As with data caches, the farther a request has to go to be satisfied, the worse the performance impact. This metric estimates the performance penalty of page walks induced on ITLB (instruction TLB) misses.
A significant proportion of cycles is spent handling instruction TLB misses. Use profile-guided optimization and IPO to reduce the size of hot code regions. Consider compiler options to reorder functions so that hot functions are located together. If your application makes significant use of macros, try to reduce this by either converting the relevant macros to functions or using linker options to eliminate repeated code. For Windows targets, add function splitting. Using large code pages may be considered here.