Intel® Fortran Compiler 16.0 User and Reference Guide
Intel® Fortran provides OpenMP* Fortran compiler directives that comply with most of OpenMP Fortran Application Program Interface (API) specification Version 4.0 and some of Version 4.1. The user-defined reduction feature of OpenMP 4.0 is not yet implemented.
To use these directives, you must specify compiler option [q or Q]openmp.
Options that use OpenMP* are available for both Intel® microprocessors and non-Intel microprocessors, but these options may perform additional optimizations on Intel® microprocessors than they perform on non-Intel microprocessors. The list of major, user-visible OpenMP constructs and features that may perform differently on Intel® microprocessors vs. non-Intel microprocessors includes: locks (internal and user visible), the SINGLE construct, barriers (explicit and implicit), parallel loop scheduling, reductions, memory allocation, thread affinity, and binding.
This section discusses clauses used in multiple OpenMP* Fortran directives, conditional compilation rules, nesting and binding rules, and the following directives:
Specifies that a specific memory location is to be updated atomically.
Synchronizes all the threads in a team.
Requests concellation of the innermost enclosing region of the type specified, and causes the encountering implicit or explicit task to proceed to the end of the canceled construct.
Defines a point at which implicit or explicit tasks check to see if cancellation has been requested for the innermost enclosing region of the type specified.
Restricts access for a block of code to only one thread at a time.
Generates a SIMD procedure.
Causes the creation of a device-specific version of a named routine that can be called from a target region. This directive only applies to Intel® MIC Architecture.
Specifies that loop iterations will be executed by thread teams in the context of their implicit tasks.
DISTRIBUTE PARALLEL DO directive
Specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams.
DISTRIBUTE PARALLEL DO SIMD directive
Specifies a loop that will be executed in parallel by multiple threads that are members of multiple teams. It will be executed concurrently using SIMD instructions.
Specifies a loop that will be distributed across the master threads of the teams region. It will be executed concurrently using SIMD instructions.
Specifies that the iterations of the immediately following DO loop must be executed in parallel.
Specifies a loop that can be executed concurrently using SIMD instructions.
Specifies synchronization points where the threads in a team must have a consistent view of memory.
Specifies a block of code to be executed by the master thread of the team.
Specifies a block of code that the threads in a team must execute in the natural order of the loop iterations.
Defines a parallel region.
Defines a parallel region that contains a single DO directive.
Specifies a loop that can be executed concurrently using SIMD instructions. It provides a shortcut for specifying a PARALLEL construct containing one SIMD loop construct and no other statement.
Defines a parallel region that contains a single SECTIONS directive.
Defines a parallel region that contains a single WORKSHARE directive.
Specifies that the enclosed SECTION directives define blocks of code to be divided among threads in a team.
Requires and controls SIMD vectorization of loops.
Specifies a block of code to be executed by only one thread in a team at a time.
Creates a device data environment and executes the construct on the same device. This directive only applies to Intel® MIC Architecture.
Creates a device data environment for the extent of the region. This directive only applies to Intel® MIC Architecture.
Specifies that variables are mapped to a device data environment. This directive only applies to Intel® MIC Architecture.
Specifies that variables are unmapped from a device data environment. This directive only applies to Intel® MIC Architecture.
Creates a device data environment and executes the construct on the same device. It also creates a league of thread teams with the master thread in each team executing the structured block. This directive only applies to Intel® MIC Architecture.
Creates a device data environment and executes the construct on the same device. It also specifies that loop iterations will be shared among the master threads of all thread teams in a league created by a TEAMS construct. This directive only applies to Intel® MIC Architecture.
TARGET TEAMS DISTRIBUTE PARALLEL DO
Creates a device data environment and then executes the construct on that device. It also specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams created by a TEAMS construct. This directive only applies to Intel® MIC Architecture.
TARGET TEAMS DISTRIBUTE PARALLEL DO SIMD
Creates a device data environment and then executes the construct on that device. It also specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams created by a TEAMS construct. The loop will be distributed across the teams, which will be executed concurrently using SIMD instructions. This directive only applies to Intel® MIC Architecture.
Creates a device data environment and executes the construct on the same device. It also specifies that loop iterations will be shared among the master threads of all thread teams in a league created by a teams construct. It will be executed concurrently using SIMD instructions. This directive only applies to Intel® MIC Architecture.
Makes the list items in the device data environment consistent with their corresponding original list items. This directive only applies to Intel® MIC Architecture.
Defines a task region.
Specifies a wait for the completion of all child tasks of the current task and all of their descendant tasks.
Specifies a wait on the completion of child tasks generated since the beginning of the current task.
Specifies that the current task can be suspended at this point in favor of execution of a different task.
Creates a group of thread teams to be used in a parallel region.
Creates a league of thread teams to execute a structured block in the master thread of each team. It also specifies that loop iterations will be shared among the master threads of all thread teams in a league created by a TEAMS construct.
Creates a league of thread teams to execute a structured block in the master thread of each team. It also specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams.
TEAMS DISTRIBUTE PARALLEL DO SIMD
Creates a league of thread teams to execute a structured block in the master thread of each team. It also specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams. The loop will be distributed across the master threads of the teams region, which will be executed concurrently using SIMD instructions.
Creates a league of thread teams to execute the structured block in the master thread of each team. It also specifies a loop that will be distributed across the master threads of the teams region. The loop will be executed concurrently using SIMD instructions.
Makes named common blocks private to each thread, but global within the thread.
Divides the work of executing a block of statements or constructs into separate units.
The OpenMP parallel directives can be grouped into the categories. For more information about the categories for these directives, see OpenMP* Directives Summary.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |
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