Intel® Fortran Compiler 16.0 User and Reference Guide
The following tables list available compiler directives.
Some directives may perform differently on Intel® microprocessors than on non-Intel microprocessors.
Each general directive name is preceded by the prefix cDIR$ (or cDEC$), where c is one of the following: !, C (or c), or *; for example, !DIR$ ALIAS).
Each OpenMP* Fortran directive name is preceded by the prefix c$OMP, where c is one of the following: !, C (or c), or *; for example, !$OMP ATOMIC.
Each OFFLOAD directive name is preceded by the prefix cDIR$, where c is one of the following: !, C (or c), or *; for example, !DIR$ OFFLOAD_TRANSFER.
Name |
Description |
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Specifies an alternate external name to be used when referring to an external subprogram. |
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Provides heuristic information to the compiler optimizer. |
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Specifies that an entity in memory is aligned. |
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Applies attributes to variables and procedures. |
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Enables loop blocking for the immediately following nested DO loops. |
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Generates warning messages for undeclared variables. |
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Creates a variable whose existence can be tested during conditional compilation. |
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Suggests a location at which a DO loop may be split. |
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Marks the beginning of an alternative conditional-compilation block to an IF directive construct. |
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Marks the beginning of an alternative conditional-compilation block to an IF directive construct. |
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Marks the end of a conditional-compilation block. |
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Sets fixed-form line length. This directive has no effect on freeform code. |
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Tells the compiler to allow generation of fused multiply-add (FMA) instructions, also known as floating-point contractions. |
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Specifies that a routine should be inlined whenever the compiler can do so. |
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Uses freeform format for source code. |
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Specifies an identifier for an object module. |
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Marks the beginning of a conditional-compilation block. |
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Marks the beginning of a conditional-compilation block. |
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Specifies that the routines can be inlined. |
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Selects default integer size. |
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Assists the compiler's dependence analysis of iterative DO loops. |
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Specifies the typical trip loop count for a DO loop; this assists the optimizer. |
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Sends a character string to the standard output device. |
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Disables loop blocking for the immediately following nested DO loops. |
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(Default) Turns off warning messages for undeclared variables. |
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Disables the generation of FMA instructions. |
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(Default) Uses standard FORTRAN 77 code formatting column rules. |
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Prevents a loop from fusing with adjacent loops. |
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Specifies that a routine should not be inlined. |
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Disables auto-parallelization for an immediately following DO loop. |
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Disables optimizations for the program unit. |
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Disables a data prefetch from memory. |
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(Default) Disables a previous STRICT directive. |
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Disables the unrolling of a DO loop. |
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Disables loop unrolling and jamming. |
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Disables vectorization of a DO loop. |
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Specifies a library search path in an object file. |
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Enables optimizations for the program unit. |
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Controls whether fields in records and data items in common blocks are naturally aligned or packed on arbitrary byte boundaries. |
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Specifies the memory alignment of derived-type items. |
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Helps auto-parallelization by assisting the compiler's dependence analysis of an immediately following DO loop. |
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Hints to the compiler to prefetch data from memory. |
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Modifies certain characteristics of a common block. |
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Selects default real size. |
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Requires and controls SIMD vectorization of loops. |
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Disables Intel® Fortran features not in the language standard specified on the command line. |
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Removes a symbolic variable name created with the DEFINE directive. |
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Tells the compiler's optimizer how many times to unroll a DO loop. |
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Enables loop unrolling and jamming. |
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Overrides default heuristics for vectorization of DO loops. |
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1i64em_mic only |
To use the following directives, you must specify compiler option [q or Q]openmp. For more information, refer to the option description in the Compiler Options reference.
Name |
Description |
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Specifies that a specific memory location is to be updated atomically. |
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Synchronizes all the threads in a team. |
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Requests concellation of the innermost enclosing region of the type specified, and causes the encountering implicit or explicit task to proceed to the end of the canceled construct. |
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Defines a point at which implicit or explicit tasks check to see if cancellation has been requested for the innermost enclosing region of the type specified. |
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Restricts access for a block of code to only one thread at a time. |
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Generates a SIMD procedure. |
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Specifies that named variables, common blocks, functions, and subroutines are mapped to a device. |
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Specifies that loop iterations will be executed by thread teams in the context of their implicit tasks. |
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Specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams. |
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Specifies a loop that will be executed in parallel by multiple threads that are members of multiple teams. It will be executed concurrently using SIMD instructions. |
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Specifies a loop that will be distributed across the master threads of the teams region. It will be executed concurrently using SIMD instructions. |
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Specifies that the iterations of the immediately following DO loop must be executed in parallel. |
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Specifies a loop that can be executed concurrently using SIMD instructions. |
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Specifies synchronization points where the implementation must have a consistent view of memory. |
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Specifies a block of code to be executed by the master thread of the team. |
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Specifies a block of code to be executed sequentially. |
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Defines a parallel region. |
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Defines a parallel region that contains a single DO directive. |
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Specifies a loop that can be executed concurrently using SIMD instructions. It provides a shortcut for specifying a PARALLEL construct containing one SIMD loop construct and no other statement. |
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Defines a parallel region that contains SECTIONS directives. |
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Defines a parallel region that contains a single WORKSHARE directive. |
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Appears within a SECTIONS directive construct to indicate a block (section) of code. It is optional for the first block of code within the SECTIONS directive construct. |
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Specifies a block of code to be divided among threads in a team (a worksharing area). |
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Requires and controls SIMD vectorization of loops. |
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Specifies a block of code to be executed by only one thread in a team. |
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Creates a device data environment and executes the construct on the same device. |
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Creates a device data environment for the extent of the region. |
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Specifies that variables are mapped to a device data environment. |
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Specifies that variables are unmapped from a device data environment |
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Creates a device data environment and executes the construct on the same device. It also creates a league of thread teams with the master thread in each team executing the structured block. This directive only applies to Intel® MIC Architecture. |
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Creates a device data environment and executes the construct on the same device. It also specifies that loop iterations will be shared among the master threads of all thread teams in a league created by a TEAMS construct. This directive only applies to Intel® MIC Architecture. |
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Creates a device data environment and then executes the construct on that device. It also specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams created by a TEAMS construct. This directive only applies to Intel® MIC Architecture. |
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Creates a device data environment and then executes the construct on that device. It also specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams created by a TEAMS construct. The loop will be distributed across the teams, which will be executed concurrently using SIMD instructions. This directive only applies to Intel® MIC Architecture. |
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Creates a device data environment and executes the construct on the same device. It also specifies that loop iterations will be shared among the master threads of all thread teams in a league created by a teams construct. It will be executed concurrently using SIMD instructions. This directive only applies to Intel® MIC Architecture. |
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Makes the list items in the device data environment consistent with their corresponding original list items. |
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Defines a task region. |
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Specifies a wait for the completion of all child tasks of the current task and all of their descendant tasks. |
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Specifies a wait on the completion of child tasks generated since the beginning of the current task. |
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Specifies that the current task can be suspended in favor of execution of a different task. |
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Creates a league of thread teams to execute a structured block in the master thread of each team. It also specifies that loop iterations will be shared among the master threads of all thread teams in a league created by a TEAMS construct. |
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Creates a league of thread teams to execute a structured block in the master thread of each team. It also specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams. |
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Creates a league of thread teams to execute a structured block in the master thread of each team. It also specifies a loop that can be executed in parallel by multiple threads that are members of multiple teams. The loop will be distributed across the master threads of the teams region, which will be executed concurrently using SIMD instructions. |
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Creates a league of thread teams to execute the structured block in the master thread of each team. It also specifies a loop that will be distributed across the master threads of the teams region. The loop will be executed concurrently using SIMD instructions. |
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Makes named common blocks private to a thread but global within the thread. |
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Divides the work of executing a block of statements or constructs into separate units. |
Name |
Description |
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Enables statements to execute on the target. |
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Enables a group of statements to execute on the target. |
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Initiates asynchronous data transfer, or initiates and completes synchronous data transfer. |
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Specifies a wait for a previously initiated asynchronous activity. |
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |