Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help
This section provides reference for hardware events that can be monitored for the CPU(s):
The following performance-monitoring events are supported:
Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)
Note that a whole rep string only counts AVX_INST.ALL once.
Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
Speculative and retired branches
Speculative and retired macro-conditional branches
Speculative and retired macro-unconditional branches excluding calls and indirects
Speculative and retired direct near calls
Speculative and retired indirect branches excluding calls and returns
Speculative and retired indirect return branches.
Not taken macro-conditional branches
Taken speculative and retired macro-conditional branches
Taken speculative and retired macro-conditional branch instructions excluding calls and indirects
Taken speculative and retired direct near calls
Taken speculative and retired indirect branches excluding calls and returns
Taken speculative and retired indirect calls
Taken speculative and retired indirect branches with return mnemonic
All (macro) branch instructions retired.
All (macro) branch instructions retired.
Conditional branch instructions retired.
Conditional branch instructions retired.
Far branch instructions retired.
Direct and indirect near call instructions retired.
Direct and indirect near call instructions retired.
Direct and indirect macro near call instructions retired (captured in ring 3).
Direct and indirect macro near call instructions retired (captured in ring 3).
Return instructions retired.
Return instructions retired.
Taken branch instructions retired.
Taken branch instructions retired.
Not taken branch instructions retired.
Speculative and retired mispredicted macro conditional branches
Speculative and retired mispredicted macro conditional branches
Mispredicted indirect branches excluding calls and returns
Not taken speculative and retired mispredicted macro conditional branches
Taken speculative and retired mispredicted macro conditional branches
Taken speculative and retired mispredicted indirect branches excluding calls and returns
Taken speculative and retired mispredicted indirect calls
Taken speculative and retired mispredicted indirect branches with return mnemonic
All mispredicted macro branch instructions retired.
This event counts all mispredicted branch instructions retired. This is a precise event.
Mispredicted conditional branch instructions retired.
Mispredicted conditional branch instructions retired.
number of near branch instructions retired that were mispredicted and taken.
number of near branch instructions retired that were mispredicted and taken.
Unhalted core cycles when the thread is in ring 0
Number of intervals between processor halts while thread is in ring 0
Unhalted core cycles when thread is in rings 1, 2, or 3
Count XClk pulses when this thread is unhalted and the other thread is halted.
Reference cycles when the thread is unhalted (counts at 100 MHz rate)
Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)
This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.
This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.
Core cycles when at least one thread on the physical core is not in halt state
Thread cycles when thread is not in halt state
Core cycles when at least one thread on the physical core is not in halt state
Cycles with pending L1 cache miss loads.
Cycles with pending L2 cache miss loads.
Cycles with pending memory loads.
This event counts cycles during which no instructions were executed in the execution stage of the pipeline.
Execution stalls due to L1 data cache misses
Execution stalls due to L2 cache misses.
This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).
Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.
Load misses in all DTLB levels that cause page walks
DTLB demand load misses with low part of linear-to-physical address translation missed
Load operations that miss the first DTLB level but hit the second and do not cause page walks
This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.
This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).
This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.
Store misses in all DTLB levels that cause page walks
DTLB store misses with low part of linear-to-physical address translation missed
Store operations that miss the first TLB level but hit the second and do not cause page walks
This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.
This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.
Store misses in all DTLB levels that cause completed page walks
Store misses in all DTLB levels that cause completed page walks (2M/4M)
Store miss in all TLB levels causes a page walk that completes. (4K)
This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.
Cycle count for an Extended Page table walk.
Cycles with any input/output SSE or FP assist
Number of SIMD FP assists due to input values
Number of SIMD FP assists due to Output values
Number of X87 assists due to input value.
Number of X87 assists due to output value.
Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).
Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).
Number of times an HLE execution aborted due to uncommon conditions
Number of times an HLE execution aborted due to HLE-unfriendly instructions
Number of times an HLE execution aborted due to incompatible memory type
Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)
Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).
Number of times an HLE execution successfully committed
Number of times an HLE execution started.
Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches
Cycles where a code fetch is stalled due to L1 instruction-cache miss.
Cycles where a code fetch is stalled due to L1 instruction-cache miss.
This event counts Instruction Cache (ICACHE) misses.
Cycles Decode Stream Buffer (DSB) is delivering 4 Uops
Cycles Decode Stream Buffer (DSB) is delivering any Uop
Cycles MITE is delivering 4 Uops
Cycles MITE is delivering any Uop
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path
Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path
Instruction Decode Queue (IDQ) empty cycles
Uops delivered to Instruction Decode Queue (IDQ) from MITE path
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path
Uops delivered to Instruction Decode Queue (IDQ) from MITE path
This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.
Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy
Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer
This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.
This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.
This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
Cycles with less than 2 uops delivered by the front end.
Cycles with less than 3 uops delivered by the front end.
Stall cycles because IQ is full
This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).
This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.
Number of instructions retired. General Counter - architectural event
Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution
This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.
This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc....
Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)
Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.
Misses at all ITLB levels that cause page walks
Operations that miss the first ITLB level but hit the second and do not cause any page walks
Code misses that miss the DTLB and hit the STLB (2M)
Core misses that miss the DTLB and hit the STLB (4K)
Misses in all ITLB levels that cause completed page walks
Code miss in all TLB levels causes a page walk that completes. (2M/4M)
Code miss in all TLB levels causes a page walk that completes. (4K)
This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.
This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.
Cycles a demand request was blocked due to Fill Buffers inavailability
L1D miss oustandings duration in cycles
Cycles with L1D load Misses outstanding.
Cycles with L1D load Misses outstanding from any thread on physical core
Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e
Not rejected writebacks that hit L2 cache
This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.
L2 cache lines in E state filling L2
L2 cache lines in I state filling L2
L2 cache lines in S state filling L2
Clean L2 cache lines evicted by demand
Dirty L2 cache lines evicted by demand
L2 code requests
Demand Data Read requests
Demand requests that miss L2 cache
Demand requests to L2 cache
Requests from L2 hardware prefetchers
RFO requests to L2 cache
L2 cache hits when fetching instructions, code reads.
L2 cache misses when fetching instructions
Demand Data Read requests that hit L2 cache
Demand Data Read miss L2, no rejects
L2 prefetch requests that hit L2 cache
L2 prefetch requests that miss L2 cache
All requests that miss L2 cache
All L2 requests
RFO requests that hit L2 cache
RFO requests that miss L2 cache
L2 or L3 HW prefetches that access L2 cache
Transactions accessing L2 pipe
L2 cache accesses when fetching instructions
Demand Data Read requests that access L2 cache
L1D writebacks that access L2 cache
L2 fill requests that access L2 cache
L2 writebacks that access L2 cache
RFO requests that access L2 cache
The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use
This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.
Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.
Not software-prefetch load dispatches that hit FB allocated for hardware prefetch
Not software-prefetch load dispatches that hit FB allocated for software prefetch
Cycles when L1D is locked
Cycles when L1 and L2 are locked due to UC or split lock
Core-originated cacheable demand requests missed L3
Core-originated cacheable demand requests that refer to L3
Cycles 4 Uops delivered by the LSD, but didn't come from the decoder
Cycles Uops delivered by the LSD, but didn't come from the decoder
Number of Uops delivered by the LSD.
Number of machine clears (nukes) of any type.
Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.
This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.
This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.
Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.
Retired load uops which data sources were HitM responses from shared L3.
This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.
This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.
Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.
Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.
Retired load uops which data sources were hits in L3 without snoops required.
Retired load uops which data sources were hits in L3 without snoops required.
This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.
This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.
Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)
Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)
Retired load uop whose Data Source was: forwarded from remote cache
tbd
Retired load uop whose Data Source was: Remote cache HITM
Retired load uop whose Data Source was: Remote cache HITM (Precise Event)
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
Retired load uops with L1 cache hits as data sources.
Retired load uops with L1 cache hits as data sources.
Retired load uops misses in L1 cache as data sources.
This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.
Retired load uops with L2 cache hits as data sources.
Retired load uops with L2 cache hits as data sources.
Miss in mid-level (L2) cache. Excludes Unknown data-source.
Retired load uops with L2 cache misses as data sources.
Retired load uops which data sources were data hits in L3 without snoops required.
This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.
Miss in last-level (L3) cache. Excludes Unknown data-source.
Miss in last-level (L3) cache. Excludes Unknown data-source.
Loads with latency value being above 128
Loads with latency value being above 16
Loads with latency value being above 256
Loads with latency value being above 32
Loads with latency value being above 4
Loads with latency value being above 512
Loads with latency value being above 64
Loads with latency value being above 8
All retired load uops.
All retired load uops. (precise Event)
All retired store uops.
This event counts all store uops retired. This is a precise event.
Retired load uops with locked access.
Retired load uops with locked access. (precise Event)
Retired load uops that split across a cacheline boundary.
This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.
Retired store uops that split across a cacheline boundary.
This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.
Retired load uops that miss the STLB.
Retired load uops that miss the STLB. (precise Event)
Retired store uops that miss the STLB.
Retired store uops that miss the STLB. (precise Event)
Speculative cache line split load uops dispatched to L1 cache
Speculative cache line split STA uops dispatched to L1 cache
Number of integer Move Elimination candidate uops that were eliminated.
Number of integer Move Elimination candidate uops that were not eliminated.
Number of SIMD Move Elimination candidate uops that were eliminated.
Number of SIMD Move Elimination candidate uops that were not eliminated.
Demand and prefetch data reads
Cacheable and noncachaeble code read requests
Demand Data Read requests sent to uncore
Demand RFO requests including regular RFOs, locks, ItoM
Offcore requests buffer cannot take more entries for this thread core.
Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore
Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore
Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore
Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle
Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle
Offcore outstanding Demand Data Read transactions in uncore queue.
Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue
Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore
Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction
Counts all demand & prefetch code reads that hit in the L3
Counts all demand & prefetch code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand & prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand & prefetch code reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all demand & prefetch code reads that miss the L3 and the data is returned from local or remote dram
Counts all demand & prefetch code reads that miss in the L3
Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram
Counts all demand & prefetch code reads that miss the L3 and the data is returned from remote dram
Counts all demand & prefetch code reads that miss the L3 and the modified data is transferred from remote cache
Counts all demand & prefetch code reads that miss the L3 and clean or shared data is transferred from remote cache
Counts all demand & prefetch data reads that hit in the L3
Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand & prefetch data reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram
Counts all demand & prefetch data reads that miss in the L3
Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram
Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram
Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache
Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache
Counts all prefetch code reads that hit in the L3
Counts all prefetch code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch code reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all prefetch code reads that miss the L3 and the data is returned from local or remote dram
Counts all prefetch code reads that miss in the L3
Counts all prefetch code reads that miss the L3 and the data is returned from local dram
Counts all prefetch code reads that miss the L3 and the data is returned from remote dram
Counts all prefetch code reads that miss the L3 and the modified data is transferred from remote cache
Counts all prefetch code reads that miss the L3 and clean or shared data is transferred from remote cache
Counts all prefetch data reads that hit in the L3
Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch data reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram
Counts all prefetch data reads that miss in the L3
Counts all prefetch data reads that miss the L3 and the data is returned from local dram
Counts all prefetch data reads that miss the L3 and the data is returned from remote dram
Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache
Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache
Counts prefetch RFOs that hit in the L3
Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch RFOs that hit in the L3 and the snoops sent to sibling cores return clean response
Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram
Counts prefetch RFOs that miss in the L3
Counts prefetch RFOs that miss the L3 and the data is returned from local dram
Counts prefetch RFOs that miss the L3 and the data is returned from remote dram
Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache
Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local or remote dram
Counts all data/code/rfo reads (demand & prefetch) that miss in the L3
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache
Counts all requests that hit in the L3
Counts all requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all requests that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all requests that miss the L3 and the data is returned from local or remote dram
Counts all requests that miss in the L3
Counts all requests that miss the L3 and the data is returned from local dram
Counts all requests that miss the L3 and the data is returned from remote dram
Counts all requests that miss the L3 and the modified data is transferred from remote cache
Counts all requests that miss the L3 and clean or shared data is transferred from remote cache
Counts all demand & prefetch RFOs that hit in the L3
Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand & prefetch RFOs that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram
Counts all demand & prefetch RFOs that miss in the L3
Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram
Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram
Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache
Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache
Counts writebacks (modified to exclusive) that hit in the L3
Counts writebacks (modified to exclusive) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts writebacks (modified to exclusive) that hit in the L3 and the snoops sent to sibling cores return clean response
Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from local or remote dram
Counts writebacks (modified to exclusive) that miss in the L3
Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from local dram
Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from remote dram
Counts writebacks (modified to exclusive) that miss the L3 and the modified data is transferred from remote cache
Counts writebacks (modified to exclusive) that miss the L3 and clean or shared data is transferred from remote cache
Counts all demand code reads that hit in the L3
Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand code reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all demand code reads that miss the L3 and the data is returned from local or remote dram
Counts all demand code reads that miss in the L3
Counts all demand code reads that miss the L3 and the data is returned from local dram
Counts all demand code reads that miss the L3 and the data is returned from remote dram
Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache
Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache
Counts demand data reads that hit in the L3
Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts demand data reads that miss the L3 and the data is returned from local or remote dram
Counts demand data reads that miss in the L3
Counts demand data reads that miss the L3 and the data is returned from local dram
Counts demand data reads that miss the L3 and the data is returned from remote dram
Counts demand data reads that miss the L3 and the modified data is transferred from remote cache
Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache
Counts all demand data writes (RFOs) that hit in the L3
Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand data writes (RFOs) that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram
Counts all demand data writes (RFOs) that miss in the L3
Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram
Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram
Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache
Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache
Counts any other requests that hit in the L3
Counts any other requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts any other requests that hit in the L3 and the snoops sent to sibling cores return clean response
Counts any other requests that miss the L3 and the data is returned from local or remote dram
Counts any other requests that miss in the L3
Counts any other requests that miss the L3 and the data is returned from local dram
Counts any other requests that miss the L3 and the data is returned from remote dram
Counts any other requests that miss the L3 and the modified data is transferred from remote cache
Counts any other requests that miss the L3 and clean or shared data is transferred from remote cache
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local or remote dram
Counts all prefetch (that bring data to LLC only) code reads that miss in the L3
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local dram
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from remote dram
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the modified data is transferred from remote cache
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and clean or shared data is transferred from remote cache
Counts prefetch (that bring data to L2) data reads that hit in the L3
Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram
Counts prefetch (that bring data to L2) data reads that miss in the L3
Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram
Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram
Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache
Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache
Counts all prefetch (that bring data to L2) RFOs that hit in the L3
Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram
Counts all prefetch (that bring data to L2) RFOs that miss in the L3
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache
Counts prefetch (that bring data to LLC only) code reads that hit in the L3
Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local or remote dram
Counts prefetch (that bring data to LLC only) code reads that miss in the L3
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local dram
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from remote dram
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the modified data is transferred from remote cache
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and clean or shared data is transferred from remote cache
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram
Counts all prefetch (that bring data to LLC only) data reads that miss in the L3
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram
Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache
Number of times any microcode assist is invoked by HW upon uop writeback.
Number of transitions from AVX-256 to legacy SSE when penalty applicable.
Number of transitions from SSE to AVX-256 when penalty applicable.
Number of DTLB page walker hits in the L1+FB
Number of DTLB page walker hits in the L2
Number of DTLB page walker hits in the L3 + XSNP
Number of DTLB page walker hits in Memory
Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.
Counts the number of Extended Page Table walks from the DTLB that hit in the L2.
Counts the number of Extended Page Table walks from the DTLB that hit in the L3.
Counts the number of Extended Page Table walks from the DTLB that hit in memory.
Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.
Counts the number of Extended Page Table walks from the ITLB that hit in the L2.
Counts the number of Extended Page Table walks from the ITLB that hit in the L2.
Counts the number of Extended Page Table walks from the ITLB that hit in memory.
Number of ITLB page walker hits in the L1+FB
Number of ITLB page walker hits in the L2
Number of ITLB page walker hits in the L3 + XSNP
Number of ITLB page walker hits in Memory
Resource-related stall cycles
Cycles stalled due to re-order buffer full.
Cycles stalled due to no eligible RS entry available.
This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.
Count cases of saving new LBR
This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).
Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)
Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).
Number of times an RTM execution aborted due to HLE-unfriendly instructions
Number of times an RTM execution aborted due to incompatible memory type
Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)
Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).
Number of times an RTM execution successfully committed
Number of times an RTM execution started.
DTLB flush attempts of the thread-specific entries
STLB flush attempts
Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.
Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region
Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded
Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.
Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region
Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.
Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address
Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer
Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.
Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.
Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer
Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.
Bounce Control
Uncore Clocks
Counter 0 Occupancy
FaST wire asserted
Cache Lookups; Any Request
Cache Lookups; Data Read Request
Cache Lookups; Lookups that Match NID
Cache Lookups; Any Read Request
Cache Lookups; External Snoop Request
Cache Lookups; Write Requests
Lines Victimized; Lines in E state
Lines Victimized
Lines Victimized; Lines in S State
Lines Victimized
Lines Victimized; Lines in M state
Lines Victimized; Victimized Lines that Match NID
Lines in S State
Cbo Misc; DRd hitting non-M with raw CV=0
Cbo Misc; Clean Victim with raw CV=0
Cbo Misc; RFO HitS
Cbo Misc; Silent Snoop Eviction
Cbo Misc
Cbo Misc; Write Combining Aliasing
LRU Queue; LRU Age 0
LRU Queue; LRU Age 1
LRU Queue; LRU Age 2
LRU Queue; LRU Age 3
LRU Queue; LRU Bits Decremented
LRU Queue; Non-0 Aged Victim
AD Ring In Use; All
AD Ring In Use; Down
AD Ring In Use; Down and Even
AD Ring In Use; Down and Odd
AD Ring In Use; Up
AD Ring In Use; Up and Even
AD Ring In Use; Up and Odd
AK Ring In Use; All
AK Ring In Use; Down
AK Ring In Use; Down and Even
AK Ring In Use; Down and Odd
AK Ring In Use; Up
AK Ring In Use; Up and Even
AK Ring In Use; Up and Odd
BL Ring in Use; Down
BL Ring in Use; Down
BL Ring in Use; Down and Even
BL Ring in Use; Down and Odd
BL Ring in Use; Up
BL Ring in Use; Up and Even
BL Ring in Use; Up and Odd
Number of LLC responses that bounced on the Ring.; AD
Number of LLC responses that bounced on the Ring.; AK
Number of LLC responses that bounced on the Ring.; BL
Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.
BL Ring in Use; Any
BL Ring in Use; Any
BL Ring in Use; Down
BL Ring in Use; Any
AD
AK
BL
IV
Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.
Ingress Arbiter Blocking Cycles; IRQ
Ingress Arbiter Blocking Cycles; IPQ
Ingress Arbiter Blocking Cycles; ISMQ_BID
Ingress Arbiter Blocking Cycles; PRQ
Ingress Allocations; IPQ
Ingress Allocations; IRQ
Ingress Allocations; IRQ Rejected
Ingress Allocations; PRQ
Ingress Allocations; PRQ
Ingress Internal Starvation Cycles; IPQ
Ingress Internal Starvation Cycles; IRQ
Ingress Internal Starvation Cycles; ISMQ
Ingress Internal Starvation Cycles; PRQ
Probe Queue Retries; Address Conflict
Probe Queue Retries; Any Reject
Probe Queue Retries; No Egress Credits
Probe Queue Retries; No QPI Credits
Probe Queue Retries; No AD Sbo Credits
Probe Queue Retries; Target Node Filter
Ingress Request Queue Rejects; Address Conflict
Ingress Request Queue Rejects; Any Reject
Ingress Request Queue Rejects; No Egress Credits
Ingress Request Queue Rejects; No IIO Credits
Ingress Request Queue Rejects
Ingress Request Queue Rejects; No QPI Credits
Ingress Request Queue Rejects; No RTIDs
Ingress Request Queue Rejects; No AD Sbo Credits
Ingress Request Queue Rejects; No BL Sbo Credits
Ingress Request Queue Rejects; Target Node Filter
ISMQ Retries; Any Reject
ISMQ Retries; No Egress Credits
ISMQ Retries; No IIO Credits
ISMQ Retries
ISMQ Retries; No QPI Credits
ISMQ Retries; No RTIDs
ISMQ Retries
ISMQ Request Queue Rejects; No AD Sbo Credits
ISMQ Request Queue Rejects; No BL Sbo Credits
ISMQ Request Queue Rejects; Target Node Filter
Ingress Occupancy; IPQ
Ingress Occupancy; IRQ
Ingress Occupancy; IRQ Rejected
Ingress Occupancy; PRQ Rejects
SBo Credits Acquired; For AD Ring
SBo Credits Acquired; For BL Ring
SBo Credits Occupancy; For AD Ring
SBo Credits Occupancy; For BL Ring
TOR Inserts; All
TOR Inserts; Evictions
TOR Inserts; Local Memory
TOR Inserts; Local Memory - Opcode Matched
TOR Inserts; Misses to Local Memory
TOR Inserts; Misses to Local Memory - Opcode Matched
TOR Inserts; Miss Opcode Match
TOR Inserts; Misses to Remote Memory
TOR Inserts; Misses to Remote Memory - Opcode Matched
TOR Inserts; NID Matched
TOR Inserts; NID Matched Evictions
TOR Inserts; NID Matched Miss All
TOR Inserts; NID and Opcode Matched Miss
TOR Inserts; NID and Opcode Matched
TOR Inserts; NID Matched Writebacks
TOR Inserts; Opcode Match
TOR Inserts; Remote Memory
TOR Inserts; Remote Memory - Opcode Matched
TOR Inserts; Writebacks
TOR Occupancy; Any
TOR Occupancy; Evictions
TOR Occupancy
TOR Occupancy; Local Memory - Opcode Matched
TOR Occupancy; Miss All
TOR Occupancy
TOR Occupancy; Misses to Local Memory - Opcode Matched
TOR Occupancy; Miss Opcode Match
TOR Occupancy
TOR Occupancy; Misses to Remote Memory - Opcode Matched
TOR Occupancy; NID Matched
TOR Occupancy; NID Matched Evictions
TOR Occupancy; NID Matched
TOR Occupancy; NID and Opcode Matched Miss
TOR Occupancy; NID and Opcode Matched
TOR Occupancy; NID Matched Writebacks
TOR Occupancy; Opcode Match
TOR Occupancy
TOR Occupancy; Remote Memory - Opcode Matched
TOR Occupancy; Writebacks
Onto AD Ring
Onto AK Ring
Onto BL Ring
Egress Allocations; AD - Cachebo
Egress Allocations; AD - Corebo
Egress Allocations; AK - Cachebo
Egress Allocations; AK - Corebo
Egress Allocations; BL - Cacheno
Egress Allocations; BL - Corebo
Egress Allocations; IV - Cachebo
Injection Starvation; Onto AD Ring (to core)
Injection Starvation; Onto AK Ring
Injection Starvation; Onto BL Ring
Injection Starvation; Onto IV Ring
QPI Address/Opcode Match; AD Opcodes
QPI Address/Opcode Match; Address
QPI Address/Opcode Match; AK Opcodes
QPI Address/Opcode Match; BL Opcodes
QPI Address/Opcode Match; Address & Opcode Match
QPI Address/Opcode Match; Opcode
BT Cycles Not Empty
BT to HT Not Issued; Incoming Data Hazard
BT to HT Not Issued; Incoming Snoop Hazard
BT to HT Not Issued; Incoming Data Hazard
BT to HT Not Issued; Incoming Data Hazard
HA to iMC Bypass; Not Taken
HA to iMC Bypass; Taken
uclks
Direct2Core Messages Sent
Cycles when Direct2Core was Disabled
Number of Reads that had Direct2Core Overridden
Directory Lat Opt Return
Directory Lookups; Snoop Not Needed
Directory Lookups; Snoop Needed
Directory Updates; Any Directory Update
Directory Updates; Directory Clear
Directory Updates; Directory Set
Counts Number of Hits in HitMe Cache; op is AckCnfltWbI
Counts Number of Hits in HitMe Cache; All Requests
Counts Number of Hits in HitMe Cache; Allocations
Counts Number of Hits in HitMe Cache; Allocations
Counts Number of Hits in HitMe Cache; HOM Requests
Counts Number of Hits in HitMe Cache; Invalidations
Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE
Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI
Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request
Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request
Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb
Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS
Counts Number of Hits in HitMe Cache; op is WbMtoI
Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI
Accumulates Number of PV bits set on HitMe Cache Hits; All Requests
Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests
Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE
Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI
Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request
Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request
Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb
Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS
Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI
Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI
Counts Number of times HitMe Cache is accessed; All Requests
Counts Number of times HitMe Cache is accessed; Allocations
Counts Number of times HitMe Cache is accessed; HOM Requests
Counts Number of times HitMe Cache is accessed; Invalidations
Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE
Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI
Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request
Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request
Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb
Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS
Counts Number of times HitMe Cache is accessed; op is WbMtoI
Cycles without QPI Ingress Credits; AD to QPI Link 0
Cycles without QPI Ingress Credits; AD to QPI Link 1
Cycles without QPI Ingress Credits; BL to QPI Link 0
Cycles without QPI Ingress Credits; BL to QPI Link 0
Cycles without QPI Ingress Credits; BL to QPI Link 1
Cycles without QPI Ingress Credits; BL to QPI Link 1
HA to iMC Normal Priority Reads Issued; Normal Priority
Retry Events
HA to iMC Full Line Writes Issued; All Writes
HA to iMC Full Line Writes Issued; Full Line Non-ISOCH
HA to iMC Full Line Writes Issued; ISOCH Full Line
HA to iMC Full Line Writes Issued; Partial Non-ISOCH
HA to iMC Full Line Writes Issued; ISOCH Partial
IOT Backpressure
IOT Backpressure
IOT Common Trigger Sequencer - Lo
IOT Common Trigger Sequencer - Lo
IOT Common Trigger Sequencer - Hi
IOT Common Trigger Sequencer - Hi
IOT Common Trigger Sequencer - Lo
IOT Common Trigger Sequencer - Lo
OSB Snoop Broadcast; Cancelled
OSB Snoop Broadcast; Local InvItoE
OSB Snoop Broadcast; Local Reads
OSB Snoop Broadcast; Reads Local - Useful
OSB Snoop Broadcast; Remote
OSB Snoop Broadcast; Remote - Useful
OSB Early Data Return; All
OSB Early Data Return; Reads to Local I
OSB Early Data Return; Reads to Local S
OSB Early Data Return; Reads to Remote I
OSB Early Data Return; Reads to Remote S
Read and Write Requests; Local InvItoEs
Read and Write Requests; Remote InvItoEs
Read and Write Requests; Reads
Read and Write Requests; Local Reads
Read and Write Requests; Remote Reads
Read and Write Requests; Writes
Read and Write Requests; Local Writes
Read and Write Requests; Remote Writes
HA AD Ring in Use; Counterclockwise
HA AD Ring in Use; Counterclockwise and Even
HA AD Ring in Use; Counterclockwise and Odd
HA AD Ring in Use; Clockwise
HA AD Ring in Use; Clockwise and Even
HA AD Ring in Use; Clockwise and Odd
HA AK Ring in Use; Counterclockwise
HA AK Ring in Use; Counterclockwise and Even
HA AK Ring in Use; Counterclockwise and Odd
HA AK Ring in Use; Clockwise
HA AK Ring in Use; Clockwise and Even
HA AK Ring in Use; Clockwise and Odd
HA BL Ring in Use; Counterclockwise
HA BL Ring in Use; Counterclockwise and Even
HA BL Ring in Use; Counterclockwise and Odd
HA BL Ring in Use; Clockwise
HA BL Ring in Use; Clockwise and Even
HA BL Ring in Use; Clockwise and Odd
iMC RPQ Credits Empty - Regular; Channel 0
iMC RPQ Credits Empty - Regular; Channel 1
iMC RPQ Credits Empty - Regular; Channel 2
iMC RPQ Credits Empty - Regular; Channel 3
iMC RPQ Credits Empty - Special; Channel 0
iMC RPQ Credits Empty - Special; Channel 1
iMC RPQ Credits Empty - Special; Channel 2
iMC RPQ Credits Empty - Special; Channel 3
SBo0 Credits Acquired; For AD Ring
SBo0 Credits Acquired; For BL Ring
SBo0 Credits Occupancy; For AD Ring
SBo0 Credits Occupancy; For BL Ring
SBo1 Credits Acquired; For AD Ring
SBo1 Credits Acquired; For BL Ring
SBo1 Credits Occupancy; For AD Ring
SBo1 Credits Occupancy; For BL Ring
Data beat the Snoop Responses; Local Requests
Data beat the Snoop Responses; Remote Requests
Cycles with Snoops Outstanding; All Requests
Cycles with Snoops Outstanding; Local Requests
Cycles with Snoops Outstanding; Remote Requests
Tracker Snoops Outstanding Accumulator; Local Requests
Tracker Snoops Outstanding Accumulator; Remote Requests
Snoop Responses Received; RSPCNFLCT*
Snoop Responses Received; RspI
Snoop Responses Received; RspIFwd
Snoop Responses Received; RspS
Snoop Responses Received; RspSFwd
Snoop Responses Received; Rsp*Fwd*WB
Snoop Responses Received; Rsp*WB
Snoop Responses Received Local; Other
Snoop Responses Received Local; RspCnflct
Snoop Responses Received Local; RspI
Snoop Responses Received Local; RspIFwd
Snoop Responses Received Local; RspS
Snoop Responses Received Local; RspSFwd
Snoop Responses Received Local; Rsp*FWD*WB
Snoop Responses Received Local; Rsp*WB
Stall on No Sbo Credits; For SBo0, AD Ring
Stall on No Sbo Credits; For SBo0, BL Ring
Stall on No Sbo Credits; For SBo1, AD Ring
Stall on No Sbo Credits; For SBo1, BL Ring
HA Requests to a TAD Region - Group 0; TAD Region 0
HA Requests to a TAD Region - Group 0; TAD Region 1
HA Requests to a TAD Region - Group 0; TAD Region 2
HA Requests to a TAD Region - Group 0; TAD Region 3
HA Requests to a TAD Region - Group 0; TAD Region 4
HA Requests to a TAD Region - Group 0; TAD Region 5
HA Requests to a TAD Region - Group 0; TAD Region 6
HA Requests to a TAD Region - Group 0; TAD Region 7
HA Requests to a TAD Region - Group 1; TAD Region 10
HA Requests to a TAD Region - Group 1; TAD Region 11
HA Requests to a TAD Region - Group 1; TAD Region 8
HA Requests to a TAD Region - Group 1; TAD Region 9
Tracker Cycles Full; Cycles Completely Used
Tracker Cycles Full; Cycles GP Completely Used
Tracker Cycles Not Empty; All Requests
Tracker Cycles Not Empty; Local Requests
Tracker Cycles Not Empty; Remote Requests
Tracker Occupancy Accumultor; Local InvItoE Requests
Tracker Occupancy Accumultor; Remote InvItoE Requests
Tracker Occupancy Accumultor; Local Read Requests
Tracker Occupancy Accumultor; Remote Read Requests
Tracker Occupancy Accumultor; Local Write Requests
Tracker Occupancy Accumultor; Remote Write Requests
Data Pending Occupancy Accumultor; Local Requests
Data Pending Occupancy Accumultor; Remote Requests
Outbound NDR Ring Transactions; Non-data Responses
AD Egress Full; All
AD Egress Full; Scheduler 0
AD Egress Full; Scheduler 1
AD Egress Not Empty; All
AD Egress Not Empty; Scheduler 0
AD Egress Not Empty; Scheduler 1
AD Egress Allocations; All
AD Egress Allocations; Scheduler 0
AD Egress Allocations; Scheduler 1
AK Egress Full; All
AK Egress Full; Scheduler 0
AK Egress Full; Scheduler 1
AK Egress Not Empty; All
AK Egress Not Empty; Scheduler 0
AK Egress Not Empty; Scheduler 1
AK Egress Allocations; All
AK Egress Allocations; Scheduler 0
AK Egress Allocations; Scheduler 1
Outbound DRS Ring Transactions to Cache; Data to Cache
Outbound DRS Ring Transactions to Cache; Data to Core
Outbound DRS Ring Transactions to Cache; Data to QPI
BL Egress Full; All
BL Egress Full; Scheduler 0
BL Egress Full; Scheduler 1
BL Egress Not Empty; All
BL Egress Not Empty; Scheduler 0
BL Egress Not Empty; Scheduler 1
BL Egress Allocations; All
BL Egress Allocations; Scheduler 0
BL Egress Allocations; Scheduler 1
Injection Starvation; For AK Ring
Injection Starvation; For BL Ring
HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0
HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1
HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2
HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3
HA iMC CHN0 WPQ Credits Empty - Special; Channel 0
HA iMC CHN0 WPQ Credits Empty - Special; Channel 1
HA iMC CHN0 WPQ Credits Empty - Special; Channel 2
HA iMC CHN0 WPQ Credits Empty - Special; Channel 3
Total Write Cache Occupancy; Any Source
Total Write Cache Occupancy; Select Source
Clocks in the IRP
Coherent Ops; CLFlush
Coherent Ops; CRd
Coherent Ops; DRd
Coherent Ops; PCIDCAHin5t
Coherent Ops; PCIRdCur
Coherent Ops; PCIItoM
Coherent Ops; RFO
Coherent Ops; WbMtoI
Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary
Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary
Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary
Misc Events - Set 0; Fastpath Rejects
Misc Events - Set 0; Fastpath Requests
Misc Events - Set 0; Fastpath Transfers From Primary to Secondary
Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary
Misc Events - Set 0; Prefetch TimeOut
Misc Events - Set 1; Data Throttled
Misc Events - Set 1
Misc Events - Set 1; Received Invalid
Misc Events - Set 1; Received Valid
Misc Events - Set 1; Slow Transfer of E Line
Misc Events - Set 1; Slow Transfer of I Line
Misc Events - Set 1; Slow Transfer of M Line
Misc Events - Set 1; Slow Transfer of S Line
AK Ingress Occupancy
tbd
BL Ingress Occupancy - DRS
tbd
tbd
BL Ingress Occupancy - NCB
tbd
tbd
BL Ingress Occupancy - NCS
tbd
Snoop Responses; Hit E or S
Snoop Responses; Hit I
Snoop Responses; Hit M
Snoop Responses; Miss
Snoop Responses; SnpCode
Snoop Responses; SnpData
Snoop Responses; SnpInv
Inbound Transaction Count; Atomic
Inbound Transaction Count; Select Source
Inbound Transaction Count; Other
Inbound Transaction Count; Read Prefetches
Inbound Transaction Count; Reads
Inbound Transaction Count; Writes
Inbound Transaction Count; Write Prefetches
No AD Egress Credit Stalls
No BL Egress Credit Stalls
Outbound Read Requests
Outbound Read Requests
Outbound Request Queue Occupancy
DRAM Activate Count; Activate due to Write
DRAM Activate Count; Activate due to Read
DRAM Activate Count; Activate due to Write
ACT command issued by 2 cycle bypass
CAS command issued by 2 cycle bypass
PRE command issued by 2 cycle bypass
DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)
DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)
DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)
DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM
DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued
DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM
DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)
DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode
DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode
DRAM Clockticks
DRAM Clockticks
DRAM Precharge All Commands
Number of DRAM Refreshes Issued
Number of DRAM Refreshes Issued
ECC Correctable Errors
Cycles in a Major Mode; Isoch Major Mode
Cycles in a Major Mode; Partial Major Mode
Cycles in a Major Mode; Read Major Mode
Cycles in a Major Mode; Write Major Mode
Channel DLLOFF Cycles
Channel PPD Cycles
CKE_ON_CYCLES by Rank; DIMM ID
CKE_ON_CYCLES by Rank; DIMM ID
CKE_ON_CYCLES by Rank; DIMM ID
CKE_ON_CYCLES by Rank; DIMM ID
CKE_ON_CYCLES by Rank; DIMM ID
CKE_ON_CYCLES by Rank; DIMM ID
CKE_ON_CYCLES by Rank; DIMM ID
CKE_ON_CYCLES by Rank; DIMM ID
Critical Throttle Cycles
tbd
Clock-Enabled Self-Refresh
Throttle Cycles for Rank 0; DIMM ID
Throttle Cycles for Rank 0; DIMM ID
Throttle Cycles for Rank 0; DIMM ID
Throttle Cycles for Rank 0; DIMM ID
Throttle Cycles for Rank 0; DIMM ID
Throttle Cycles for Rank 0; DIMM ID
Throttle Cycles for Rank 0; DIMM ID
Throttle Cycles for Rank 0; DIMM ID
Read Preemption Count; Read over Read Preemption
Read Preemption Count; Read over Write Preemption
DRAM Precharge commands.; Precharge due to bypass
DRAM Precharge commands.; Precharge due to timer expiration
DRAM Precharge commands.; Precharges due to page miss
DRAM Precharge commands.; Precharge due to read
DRAM Precharge commands.; Precharge due to write
Read CAS issued with HIGH priority
Read CAS issued with LOW priority
Read CAS issued with MEDIUM priority
Read CAS issued with PANIC NON ISOCH priority (starved)
RD_CAS Access to Rank 0; All Banks
RD_CAS Access to Rank 0; Bank 0
RD_CAS Access to Rank 0; Bank 1
RD_CAS Access to Rank 0; Bank 10
RD_CAS Access to Rank 0; Bank 11
RD_CAS Access to Rank 0; Bank 12
RD_CAS Access to Rank 0; Bank 13
RD_CAS Access to Rank 0; Bank 14
RD_CAS Access to Rank 0; Bank 15
RD_CAS Access to Rank 0; Bank 2
RD_CAS Access to Rank 0; Bank 3
RD_CAS Access to Rank 0; Bank 4
RD_CAS Access to Rank 0; Bank 5
RD_CAS Access to Rank 0; Bank 6
RD_CAS Access to Rank 0; Bank 7
RD_CAS Access to Rank 0; Bank 8
RD_CAS Access to Rank 0; Bank 9
RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)
RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)
RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)
RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)
RD_CAS Access to Rank 1; All Banks
RD_CAS Access to Rank 1; Bank 0
RD_CAS Access to Rank 1; Bank 1
RD_CAS Access to Rank 1; Bank 10
RD_CAS Access to Rank 1; Bank 11
RD_CAS Access to Rank 1; Bank 12
RD_CAS Access to Rank 1; Bank 13
RD_CAS Access to Rank 1; Bank 14
RD_CAS Access to Rank 1; Bank 15
RD_CAS Access to Rank 1; Bank 2
RD_CAS Access to Rank 1; Bank 3
RD_CAS Access to Rank 1; Bank 4
RD_CAS Access to Rank 1; Bank 5
RD_CAS Access to Rank 1; Bank 6
RD_CAS Access to Rank 1; Bank 7
RD_CAS Access to Rank 1; Bank 8
RD_CAS Access to Rank 1; Bank 9
RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)
RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)
RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)
RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)
RD_CAS Access to Rank 2; Bank 0
RD_CAS Access to Rank 4; All Banks
RD_CAS Access to Rank 4; Bank 0
RD_CAS Access to Rank 4; Bank 1
RD_CAS Access to Rank 4; Bank 10
RD_CAS Access to Rank 4; Bank 11
RD_CAS Access to Rank 4; Bank 12
RD_CAS Access to Rank 4; Bank 13
RD_CAS Access to Rank 4; Bank 14
RD_CAS Access to Rank 4; Bank 15
RD_CAS Access to Rank 4; Bank 2
RD_CAS Access to Rank 4; Bank 3
RD_CAS Access to Rank 4; Bank 4
RD_CAS Access to Rank 4; Bank 5
RD_CAS Access to Rank 4; Bank 6
RD_CAS Access to Rank 4; Bank 7
RD_CAS Access to Rank 4; Bank 8
RD_CAS Access to Rank 4; Bank 9
RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)
RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)
RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)
RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)
RD_CAS Access to Rank 5; All Banks
RD_CAS Access to Rank 5; Bank 0
RD_CAS Access to Rank 5; Bank 1
RD_CAS Access to Rank 5; Bank 10
RD_CAS Access to Rank 5; Bank 11
RD_CAS Access to Rank 5; Bank 12
RD_CAS Access to Rank 5; Bank 13
RD_CAS Access to Rank 5; Bank 14
RD_CAS Access to Rank 5; Bank 15
RD_CAS Access to Rank 5; Bank 2
RD_CAS Access to Rank 5; Bank 3
RD_CAS Access to Rank 5; Bank 4
RD_CAS Access to Rank 5; Bank 5
RD_CAS Access to Rank 5; Bank 6
RD_CAS Access to Rank 5; Bank 7
RD_CAS Access to Rank 5; Bank 8
RD_CAS Access to Rank 5; Bank 9
RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)
RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)
RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)
RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)
RD_CAS Access to Rank 6; All Banks
RD_CAS Access to Rank 6; Bank 0
RD_CAS Access to Rank 6; Bank 1
RD_CAS Access to Rank 6; Bank 10
RD_CAS Access to Rank 6; Bank 11
RD_CAS Access to Rank 6; Bank 12
RD_CAS Access to Rank 6; Bank 13
RD_CAS Access to Rank 6; Bank 14
RD_CAS Access to Rank 6; Bank 15
RD_CAS Access to Rank 6; Bank 2
RD_CAS Access to Rank 6; Bank 3
RD_CAS Access to Rank 6; Bank 4
RD_CAS Access to Rank 6; Bank 5
RD_CAS Access to Rank 6; Bank 6
RD_CAS Access to Rank 6; Bank 7
RD_CAS Access to Rank 6; Bank 8
RD_CAS Access to Rank 6; Bank 9
RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)
RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)
RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)
RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)
RD_CAS Access to Rank 7; All Banks
RD_CAS Access to Rank 7; Bank 0
RD_CAS Access to Rank 7; Bank 1
RD_CAS Access to Rank 7; Bank 10
RD_CAS Access to Rank 7; Bank 11
RD_CAS Access to Rank 7; Bank 12
RD_CAS Access to Rank 7; Bank 13
RD_CAS Access to Rank 7; Bank 14
RD_CAS Access to Rank 7; Bank 15
RD_CAS Access to Rank 7; Bank 2
RD_CAS Access to Rank 7; Bank 3
RD_CAS Access to Rank 7; Bank 4
RD_CAS Access to Rank 7; Bank 5
RD_CAS Access to Rank 7; Bank 6
RD_CAS Access to Rank 7; Bank 7
RD_CAS Access to Rank 7; Bank 8
RD_CAS Access to Rank 7; Bank 9
RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)
RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)
RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)
RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)
Read Pending Queue Not Empty
Read Pending Queue Allocations
VMSE MXB write buffer occupancy
VMSE WR PUSH issued; VMSE write PUSH issued in RMM
VMSE WR PUSH issued; VMSE write PUSH issued in WMM
Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter
Transition from WMM to RMM because of low threshold
Transition from WMM to RMM because of low threshold
Write Pending Queue Full Cycles
Write Pending Queue Not Empty
Write Pending Queue CAM Match
Write Pending Queue CAM Match
Not getting the requested Major Mode
WR_CAS Access to Rank 0; All Banks
WR_CAS Access to Rank 0; Bank 0
WR_CAS Access to Rank 0; Bank 1
WR_CAS Access to Rank 0; Bank 10
WR_CAS Access to Rank 0; Bank 11
WR_CAS Access to Rank 0; Bank 12
WR_CAS Access to Rank 0; Bank 13
WR_CAS Access to Rank 0; Bank 14
WR_CAS Access to Rank 0; Bank 15
WR_CAS Access to Rank 0; Bank 2
WR_CAS Access to Rank 0; Bank 3
WR_CAS Access to Rank 0; Bank 4
WR_CAS Access to Rank 0; Bank 5
WR_CAS Access to Rank 0; Bank 6
WR_CAS Access to Rank 0; Bank 7
WR_CAS Access to Rank 0; Bank 8
WR_CAS Access to Rank 0; Bank 9
WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)
WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)
WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)
WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)
WR_CAS Access to Rank 1; All Banks
WR_CAS Access to Rank 1; Bank 0
WR_CAS Access to Rank 1; Bank 1
WR_CAS Access to Rank 1; Bank 10
WR_CAS Access to Rank 1; Bank 11
WR_CAS Access to Rank 1; Bank 12
WR_CAS Access to Rank 1; Bank 13
WR_CAS Access to Rank 1; Bank 14
WR_CAS Access to Rank 1; Bank 15
WR_CAS Access to Rank 1; Bank 2
WR_CAS Access to Rank 1; Bank 3
WR_CAS Access to Rank 1; Bank 4
WR_CAS Access to Rank 1; Bank 5
WR_CAS Access to Rank 1; Bank 6
WR_CAS Access to Rank 1; Bank 7
WR_CAS Access to Rank 1; Bank 8
WR_CAS Access to Rank 1; Bank 9
WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)
WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)
WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)
WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)
WR_CAS Access to Rank 4; All Banks
WR_CAS Access to Rank 4; Bank 0
WR_CAS Access to Rank 4; Bank 1
WR_CAS Access to Rank 4; Bank 10
WR_CAS Access to Rank 4; Bank 11
WR_CAS Access to Rank 4; Bank 12
WR_CAS Access to Rank 4; Bank 13
WR_CAS Access to Rank 4; Bank 14
WR_CAS Access to Rank 4; Bank 15
WR_CAS Access to Rank 4; Bank 2
WR_CAS Access to Rank 4; Bank 3
WR_CAS Access to Rank 4; Bank 4
WR_CAS Access to Rank 4; Bank 5
WR_CAS Access to Rank 4; Bank 6
WR_CAS Access to Rank 4; Bank 7
WR_CAS Access to Rank 4; Bank 8
WR_CAS Access to Rank 4; Bank 9
WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)
WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)
WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)
WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)
WR_CAS Access to Rank 5; All Banks
WR_CAS Access to Rank 5; Bank 0
WR_CAS Access to Rank 5; Bank 1
WR_CAS Access to Rank 5; Bank 10
WR_CAS Access to Rank 5; Bank 11
WR_CAS Access to Rank 5; Bank 12
WR_CAS Access to Rank 5; Bank 13
WR_CAS Access to Rank 5; Bank 14
WR_CAS Access to Rank 5; Bank 15
WR_CAS Access to Rank 5; Bank 2
WR_CAS Access to Rank 5; Bank 3
WR_CAS Access to Rank 5; Bank 4
WR_CAS Access to Rank 5; Bank 5
WR_CAS Access to Rank 5; Bank 6
WR_CAS Access to Rank 5; Bank 7
WR_CAS Access to Rank 5; Bank 8
WR_CAS Access to Rank 5; Bank 9
WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)
WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)
WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)
WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)
WR_CAS Access to Rank 6; All Banks
WR_CAS Access to Rank 6; Bank 0
WR_CAS Access to Rank 6; Bank 1
WR_CAS Access to Rank 6; Bank 10
WR_CAS Access to Rank 6; Bank 11
WR_CAS Access to Rank 6; Bank 12
WR_CAS Access to Rank 6; Bank 13
WR_CAS Access to Rank 6; Bank 14
WR_CAS Access to Rank 6; Bank 15
WR_CAS Access to Rank 6; Bank 2
WR_CAS Access to Rank 6; Bank 3
WR_CAS Access to Rank 6; Bank 4
WR_CAS Access to Rank 6; Bank 5
WR_CAS Access to Rank 6; Bank 6
WR_CAS Access to Rank 6; Bank 7
WR_CAS Access to Rank 6; Bank 8
WR_CAS Access to Rank 6; Bank 9
WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)
WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)
WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)
WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)
WR_CAS Access to Rank 7; All Banks
WR_CAS Access to Rank 7; Bank 0
WR_CAS Access to Rank 7; Bank 1
WR_CAS Access to Rank 7; Bank 10
WR_CAS Access to Rank 7; Bank 11
WR_CAS Access to Rank 7; Bank 12
WR_CAS Access to Rank 7; Bank 13
WR_CAS Access to Rank 7; Bank 14
WR_CAS Access to Rank 7; Bank 15
WR_CAS Access to Rank 7; Bank 2
WR_CAS Access to Rank 7; Bank 3
WR_CAS Access to Rank 7; Bank 4
WR_CAS Access to Rank 7; Bank 5
WR_CAS Access to Rank 7; Bank 6
WR_CAS Access to Rank 7; Bank 7
WR_CAS Access to Rank 7; Bank 8
WR_CAS Access to Rank 7; Bank 9
WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)
WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)
WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)
WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)
pclk Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Transition Cycles
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Core C State Demotions
Frequency Residency
Frequency Residency
Frequency Residency
Frequency Residency
Thermal Strongest Upper Limit Cycles
OS Strongest Upper Limit Cycles
Power Strongest Upper Limit Cycles
IO P Limit Strongest Lower Limit Cycles
Cycles spent changing Frequency
Memory Phase Shedding Cycles
Package C State Residency - C0
Package C State Residency - C1E
Package C State Residency - C2E
Package C State Residency - C3
Package C State Residency - C6
Package C7 State Residency
Number of cores in C-State; C0 and C1
Number of cores in C-State; C3
Number of cores in C-State; C6 and C7
External Prochot
Internal Prochot
Total Core C State Transition Cycles
tbd
tbd
VR Hot
Number of qfclks
Count of CTO Events
Direct 2 Core Spawning; Spawn Failure - Egress Credits
Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss
Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid
Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid
Direct 2 Core Spawning; Spawn Failure - RBT Miss
Direct 2 Core Spawning; Spawn Failure - RBT Invalid
Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid
Direct 2 Core Spawning; Spawn Success
Cycles in L1
Cycles in L0p
Cycles in L0
Rx Flit Buffer Bypassed
CRC Errors Detected; LinkInit
CRC Errors Detected; Normal Operations
VN0 Credit Consumed; DRS
VN0 Credit Consumed; HOM
VN0 Credit Consumed; NCB
VN0 Credit Consumed; NCS
VN0 Credit Consumed; NDR
VN0 Credit Consumed; SNP
VN1 Credit Consumed; DRS
VN1 Credit Consumed; HOM
VN1 Credit Consumed; NCB
VN1 Credit Consumed; NCS
VN1 Credit Consumed; NDR
VN1 Credit Consumed; SNP
VNA Credit Consumed
RxQ Cycles Not Empty
RxQ Cycles Not Empty - DRS; for VN0
RxQ Cycles Not Empty - DRS; for VN1
RxQ Cycles Not Empty - HOM; for VN0
RxQ Cycles Not Empty - HOM; for VN1
RxQ Cycles Not Empty - NCB; for VN0
RxQ Cycles Not Empty - NCB; for VN1
RxQ Cycles Not Empty - NCS; for VN0
RxQ Cycles Not Empty - NCS; for VN1
RxQ Cycles Not Empty - NDR; for VN0
RxQ Cycles Not Empty - NDR; for VN1
RxQ Cycles Not Empty - SNP; for VN0
RxQ Cycles Not Empty - SNP; for VN1
Flits Received - Group 0; Idle and Null Flits
Flits Received - Group 1; DRS Flits (both Header and Data)
Flits Received - Group 1; DRS Data Flits
Flits Received - Group 1; DRS Header Flits
Flits Received - Group 1; HOM Flits
Flits Received - Group 1; HOM Non-Request Flits
Flits Received - Group 1; HOM Request Flits
Flits Received - Group 1; SNP Flits
Flits Received - Group 2; Non-Coherent Rx Flits
Flits Received - Group 2; Non-Coherent data Rx Flits
Flits Received - Group 2; Non-Coherent non-data Rx Flits
Flits Received - Group 2; Non-Coherent standard Rx Flits
Flits Received - Group 2; Non-Data Response Rx Flits - AD
Flits Received - Group 2; Non-Data Response Rx Flits - AK
Rx Flit Buffer Allocations
Rx Flit Buffer Allocations - DRS; for VN0
Rx Flit Buffer Allocations - DRS; for VN1
Rx Flit Buffer Allocations - HOM; for VN0
Rx Flit Buffer Allocations - HOM; for VN1
Rx Flit Buffer Allocations - NCB; for VN0
Rx Flit Buffer Allocations - NCB; for VN1
Rx Flit Buffer Allocations - NCS; for VN0
Rx Flit Buffer Allocations - NCS; for VN1
Rx Flit Buffer Allocations - NDR; for VN0
Rx Flit Buffer Allocations - NDR; for VN1
Rx Flit Buffer Allocations - SNP; for VN0
Rx Flit Buffer Allocations - SNP; for VN1
RxQ Occupancy - All Packets
RxQ Occupancy - DRS; for VN0
RxQ Occupancy - DRS; for VN1
RxQ Occupancy - HOM; for VN0
RxQ Occupancy - HOM; for VN1
RxQ Occupancy - NCB; for VN0
RxQ Occupancy - NCB; for VN1
RxQ Occupancy - NCS; for VN0
RxQ Occupancy - NCS; for VN1
RxQ Occupancy - NDR; for VN0
RxQ Occupancy - NDR; for VN1
RxQ Occupancy - SNP; for VN0
RxQ Occupancy - SNP; for VN1
Stalls Sending to R3QPI on VN0; BGF Stall - HOM
Stalls Sending to R3QPI on VN0; BGF Stall - DRS
Stalls Sending to R3QPI on VN0; BGF Stall - SNP
Stalls Sending to R3QPI on VN0; BGF Stall - NDR
Stalls Sending to R3QPI on VN0; BGF Stall - NCS
Stalls Sending to R3QPI on VN0; BGF Stall - NCB
Stalls Sending to R3QPI on VN0; Egress Credits
Stalls Sending to R3QPI on VN0; GV
Stalls Sending to R3QPI on VN1; BGF Stall - HOM
Stalls Sending to R3QPI on VN1; BGF Stall - DRS
Stalls Sending to R3QPI on VN1; BGF Stall - SNP
Stalls Sending to R3QPI on VN1; BGF Stall - NDR
Stalls Sending to R3QPI on VN1; BGF Stall - NCS
Stalls Sending to R3QPI on VN1; BGF Stall - NCB
Cycles in L0p
Cycles in L0
Tx Flit Buffer Bypassed
Cycles Stalled with no LLR Credits; LLR is almost full
Cycles Stalled with no LLR Credits; LLR is full
Tx Flit Buffer Cycles not Empty
Flits Transferred - Group 0; Data Tx Flits
Flits Transferred - Group 0; Non-Data protocol Tx Flits
Flits Transferred - Group 1; DRS Flits (both Header and Data)
Flits Transferred - Group 1; DRS Data Flits
Flits Transferred - Group 1; DRS Header Flits
Flits Transferred - Group 1; HOM Flits
Flits Transferred - Group 1; HOM Non-Request Flits
Flits Transferred - Group 1; HOM Request Flits
Flits Transferred - Group 1; SNP Flits
Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits
Flits Transferred - Group 2; Non-Coherent data Tx Flits
Flits Transferred - Group 2; Non-Coherent non-data Tx Flits
Flits Transferred - Group 2; Non-Coherent standard Tx Flits
Flits Transferred - Group 2; Non-Data Response Tx Flits - AD
Flits Transferred - Group 2; Non-Data Response Tx Flits - AK
Tx Flit Buffer Allocations
Tx Flit Buffer Occupancy
R3QPI Egress Credit Occupancy - HOM; for VN0
R3QPI Egress Credit Occupancy - HOM; for VN1
R3QPI Egress Credit Occupancy - AD HOM; for VN0
R3QPI Egress Credit Occupancy - AD HOM; for VN1
R3QPI Egress Credit Occupancy - AD NDR; for VN0
R3QPI Egress Credit Occupancy - AD NDR; for VN1
R3QPI Egress Credit Occupancy - AD NDR; for VN0
R3QPI Egress Credit Occupancy - AD NDR; for VN1
R3QPI Egress Credit Occupancy - SNP; for VN0
R3QPI Egress Credit Occupancy - SNP; for VN1
R3QPI Egress Credit Occupancy - AD SNP; for VN0
R3QPI Egress Credit Occupancy - AD SNP; for VN1
R3QPI Egress Credit Occupancy - AK NDR
R3QPI Egress Credit Occupancy - AK NDR
R3QPI Egress Credit Occupancy - DRS; for VN0
R3QPI Egress Credit Occupancy - DRS; for VN1
R3QPI Egress Credit Occupancy - DRS; for Shared VN
R3QPI Egress Credit Occupancy - BL DRS; for VN0
R3QPI Egress Credit Occupancy - BL DRS; for VN1
R3QPI Egress Credit Occupancy - BL DRS; for Shared VN
R3QPI Egress Credit Occupancy - NCB; for VN0
R3QPI Egress Credit Occupancy - NCB; for VN1
R3QPI Egress Credit Occupancy - BL NCB; for VN0
R3QPI Egress Credit Occupancy - BL NCB; for VN1
R3QPI Egress Credit Occupancy - NCS; for VN0
R3QPI Egress Credit Occupancy - NCS; for VN1
R3QPI Egress Credit Occupancy - BL NCS; for VN0
R3QPI Egress Credit Occupancy - BL NCS; for VN1
VNA Credits Returned
VNA Credits Pending Return - Occupancy
Number of uclks in domain
tbd
tbd
tbd
tbd
R2PCIe IIO Credit Acquired; DRS
R2PCIe IIO Credit Acquired; NCB
R2PCIe IIO Credit Acquired; NCS
R2PCIe IIO Credits in Use; DRS
R2PCIe IIO Credits in Use; NCB
R2PCIe IIO Credits in Use; NCS
R2 AD Ring in Use; Counterclockwise
R2 AD Ring in Use; Counterclockwise and Even
R2 AD Ring in Use; Counterclockwise and Odd
R2 AD Ring in Use; Clockwise
R2 AD Ring in Use; Clockwise and Even
R2 AD Ring in Use; Clockwise and Odd
AK Ingress Bounced; Dn
AK Ingress Bounced; Up
R2 AK Ring in Use; Counterclockwise
R2 AK Ring in Use; Counterclockwise and Even
R2 AK Ring in Use; Counterclockwise and Odd
R2 AK Ring in Use; Clockwise
R2 AK Ring in Use; Clockwise and Even
R2 AK Ring in Use; Clockwise and Odd
R2 BL Ring in Use; Counterclockwise
R2 BL Ring in Use; Counterclockwise and Even
R2 BL Ring in Use; Counterclockwise and Odd
R2 BL Ring in Use; Clockwise
R2 BL Ring in Use; Clockwise and Even
R2 BL Ring in Use; Clockwise and Odd
R2 IV Ring in Use; Any
R2 IV Ring in Use; Counterclockwise
R2 IV Ring in Use; Clockwise
Ingress Cycles Not Empty; NCB
Ingress Cycles Not Empty; NCS
Ingress Allocations; NCB
Ingress Allocations; NCS
Ingress Occupancy Accumulator; DRS
SBo0 Credits Acquired; For AD Ring
SBo0 Credits Acquired; For BL Ring
SBo0 Credits Occupancy; For AD Ring
SBo0 Credits Occupancy; For BL Ring
Stall on No Sbo Credits; For SBo0, AD Ring
Stall on No Sbo Credits; For SBo0, BL Ring
Stall on No Sbo Credits; For SBo1, AD Ring
Stall on No Sbo Credits; For SBo1, BL Ring
Egress Cycles Full; AD
Egress Cycles Full; AK
Egress Cycles Full; BL
Egress Cycles Not Empty; AD
Egress Cycles Not Empty; AK
Egress Cycles Not Empty; BL
Egress CCW NACK; AD CCW
Egress CCW NACK; AK CCW
Egress CCW NACK; BL CCW
Egress CCW NACK; AK CCW
Egress CCW NACK; BL CW
Egress CCW NACK; BL CCW
Number of uclks in domain
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
CBox AD Credits Empty
HA/R2 AD Credits Empty
HA/R2 AD Credits Empty
HA/R2 AD Credits Empty
HA/R2 AD Credits Empty
IOT Backpressure
IOT Backpressure
IOT Common Trigger Sequencer - Hi
IOT Common Trigger Sequencer - Hi
IOT Common Trigger Sequencer - Lo
IOT Common Trigger Sequencer - Lo
QPI0 AD Credits Empty
QPI0 AD Credits Empty
QPI0 AD Credits Empty
QPI0 AD Credits Empty
QPI0 AD Credits Empty
QPI0 AD Credits Empty
QPI0 AD Credits Empty
QPI0 BL Credits Empty
QPI0 BL Credits Empty
QPI0 BL Credits Empty
QPI0 BL Credits Empty
QPI1 AD Credits Empty
QPI1 AD Credits Empty
QPI1 AD Credits Empty
QPI1 AD Credits Empty
QPI1 BL Credits Empty
QPI1 BL Credits Empty
QPI1 BL Credits Empty
QPI1 BL Credits Empty
QPI1 BL Credits Empty
QPI1 BL Credits Empty
QPI1 BL Credits Empty
R3 AD Ring in Use; Counterclockwise
R3 AD Ring in Use; Counterclockwise and Even
R3 AD Ring in Use; Counterclockwise and Odd
R3 AD Ring in Use; Clockwise
R3 AD Ring in Use; Clockwise and Even
R3 AD Ring in Use; Clockwise and Odd
R3 AK Ring in Use; Counterclockwise
R3 AK Ring in Use; Counterclockwise and Even
R3 AK Ring in Use; Counterclockwise and Odd
R3 AK Ring in Use; Clockwise
R3 AK Ring in Use; Clockwise and Even
R3 AK Ring in Use; Clockwise and Odd
R3 BL Ring in Use; Counterclockwise
R3 BL Ring in Use; Counterclockwise and Even
R3 BL Ring in Use; Counterclockwise and Odd
R3 BL Ring in Use; Clockwise
R3 BL Ring in Use; Clockwise and Even
R3 BL Ring in Use; Clockwise and Odd
R3 IV Ring in Use; Any
R3 IV Ring in Use; Clockwise
Ring Stop Starved; AK
Ingress Cycles Not Empty; HOM
Ingress Cycles Not Empty; NDR
Ingress Cycles Not Empty; SNP
VN1 Ingress Cycles Not Empty; DRS
VN1 Ingress Cycles Not Empty; HOM
VN1 Ingress Cycles Not Empty; NCB
VN1 Ingress Cycles Not Empty; NCS
VN1 Ingress Cycles Not Empty; NDR
VN1 Ingress Cycles Not Empty; SNP
Ingress Allocations; DRS
Ingress Allocations; HOM
Ingress Allocations; NCB
Ingress Allocations; NCS
Ingress Allocations; NDR
Ingress Allocations; SNP
VN1 Ingress Allocations; DRS
VN1 Ingress Allocations; HOM
VN1 Ingress Allocations; NCB
VN1 Ingress Allocations; NCS
VN1 Ingress Allocations; NDR
VN1 Ingress Allocations; SNP
VN1 Ingress Occupancy Accumulator; DRS
VN1 Ingress Occupancy Accumulator; HOM
VN1 Ingress Occupancy Accumulator; NCB
VN1 Ingress Occupancy Accumulator; NCS
VN1 Ingress Occupancy Accumulator; NDR
VN1 Ingress Occupancy Accumulator; SNP
SBo0 Credits Acquired; For AD Ring
SBo0 Credits Acquired; For BL Ring
SBo0 Credits Occupancy; For AD Ring
SBo0 Credits Occupancy; For BL Ring
SBo1 Credits Acquired; For AD Ring
SBo1 Credits Acquired; For BL Ring
SBo1 Credits Occupancy; For AD Ring
SBo1 Credits Occupancy; For BL Ring
Stall on No Sbo Credits; For SBo0, AD Ring
Stall on No Sbo Credits; For SBo0, BL Ring
Stall on No Sbo Credits; For SBo1, AD Ring
Stall on No Sbo Credits; For SBo1, BL Ring
Egress CCW NACK; AD CCW
Egress CCW NACK; AK CCW
Egress CCW NACK; BL CCW
Egress CCW NACK; AK CCW
Egress CCW NACK; BL CW
Egress CCW NACK; BL CCW
VN0 Credit Acquisition Failed on DRS; DRS Message Class
VN0 Credit Acquisition Failed on DRS; HOM Message Class
VN0 Credit Acquisition Failed on DRS; NCB Message Class
VN0 Credit Acquisition Failed on DRS; NCS Message Class
VN0 Credit Acquisition Failed on DRS; NDR Message Class
VN0 Credit Acquisition Failed on DRS; SNP Message Class
VN0 Credit Used; DRS Message Class
VN0 Credit Used; HOM Message Class
VN0 Credit Used; NCB Message Class
VN0 Credit Used; NCS Message Class
VN0 Credit Used; NDR Message Class
VN0 Credit Used; SNP Message Class
VN1 Credit Acquisition Failed on DRS; DRS Message Class
VN1 Credit Acquisition Failed on DRS; HOM Message Class
VN1 Credit Acquisition Failed on DRS; NCB Message Class
VN1 Credit Acquisition Failed on DRS; NCS Message Class
VN1 Credit Acquisition Failed on DRS; NDR Message Class
VN1 Credit Acquisition Failed on DRS; SNP Message Class
VN1 Credit Used; DRS Message Class
VN1 Credit Used; HOM Message Class
VN1 Credit Used; NCB Message Class
VN1 Credit Used; NCS Message Class
VN1 Credit Used; NDR Message Class
VN1 Credit Used; SNP Message Class
VNA credit Acquisitions; HOM Message Class
VNA credit Acquisitions; HOM Message Class
VNA Credit Reject; DRS Message Class
VNA Credit Reject; HOM Message Class
VNA Credit Reject; NCB Message Class
VNA Credit Reject; NCS Message Class
VNA Credit Reject; NDR Message Class
VNA Credit Reject; SNP Message Class
Bounce Control
Uncore Clocks
FaST wire asserted
AD Ring In Use; Down
AD Ring In Use; Down and Event
AD Ring In Use; Down and Odd
AD Ring In Use; Up
AD Ring In Use; Up and Even
AD Ring In Use; Up and Odd
AK Ring In Use; Down
AK Ring In Use; Down and Event
AK Ring In Use; Down and Odd
AK Ring In Use; Up
AK Ring In Use; Up and Even
AK Ring In Use; Up and Odd
BL Ring in Use; Down
BL Ring in Use; Down and Event
BL Ring in Use; Down and Odd
BL Ring in Use; Up
BL Ring in Use; Up and Even
BL Ring in Use; Up and Odd
Number of LLC responses that bounced on the Ring.
Number of LLC responses that bounced on the Ring.; Acknowledgements to core
Number of LLC responses that bounced on the Ring.; Data Responses to core
Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.
BL Ring in Use; Any
BL Ring in Use; Any
tbd
tbd
tbd
tbd
Injection Starvation; AD - Bounces
Injection Starvation; AD - Credits
Injection Starvation; BL - Bounces
Injection Starvation; BL - Credits
Bypass; AD - Bounces
Bypass; AD - Credits
Bypass; AK
Bypass; BL - Bounces
Bypass; BL - Credits
Bypass; IV
Injection Starvation; AD - Bounces
Injection Starvation; AD - Credits
Injection Starvation; AK
Injection Starvation; BL - Bounces
Injection Starvation; BL - Credits
Injection Starvation; IVF Credit
Injection Starvation; IV
Ingress Allocations; AD - Bounces
Ingress Allocations; AD - Credits
Ingress Allocations; AK
Ingress Allocations; BL - Bounces
Ingress Allocations; BL - Credits
Ingress Allocations; IV
Ingress Occupancy; AD - Bounces
Ingress Occupancy; AD - Credits
Ingress Occupancy; AK
Ingress Occupancy; BL - Bounces
Ingress Occupancy; BL - Credits
Ingress Occupancy; IV
tbd
tbd
tbd
Egress Allocations; AD - Bounces
Egress Allocations; AD - Credits
Egress Allocations; AK
Egress Allocations; BL - Bounces
Egress Allocations; BL - Credits
Egress Allocations; IV
Egress Occupancy; AD - Bounces
Egress Occupancy; AD - Credits
Egress Occupancy; AK
Egress Occupancy; BL - Bounces
Egress Occupancy; BL - Credits
Egress Occupancy; IV
Injection Starvation; Onto AD Ring
Injection Starvation; Onto AK Ring
Injection Starvation; Onto BL Ring
Injection Starvation; Onto IV Ring
tbd
VLW Received
Filter Match
Filter Match
Filter Match
Filter Match
Cycles PHOLD Assert to Ack; Assert to ACK
RACU Request
Monitor Sent to T0; Correctable Machine Check
Monitor Sent to T0; Livelock
Monitor Sent to T0; LTError
Monitor Sent to T0; Monitor T0
Monitor Sent to T0; Monitor T1
Monitor Sent to T0; Other
Monitor Sent to T0; Trap
Monitor Sent to T0; Uncorrectable Machine Check
Cycles per thread when uops are executed in port 0
Cycles per thread when uops are executed in port 1
Cycles per thread when uops are executed in port 2
Cycles per thread when uops are executed in port 3
Cycles per thread when uops are executed in port 4
Cycles per thread when uops are executed in port 5
Cycles per thread when uops are executed in port 6
Cycles per thread when uops are executed in port 7
Number of uops executed on the core.
Cycles at least 1 micro-op is executed from any thread on physical core
Cycles at least 2 micro-op is executed from any thread on physical core
Cycles at least 3 micro-op is executed from any thread on physical core
Cycles at least 4 micro-op is executed from any thread on physical core
Cycles with no micro-ops executed from any thread on physical core
This events counts the cycles where at least one uop was executed. It is counted per thread.
This events counts the cycles where at least two uop were executed. It is counted per thread.
This events counts the cycles where at least three uop were executed. It is counted per thread.
Cycles where at least 4 uops were executed per-thread
Counts number of cycles no uops were dispatched to be executed on this thread.
Cycles per thread when uops are executed in port 0
Cycles per core when uops are exectuted in port 0
Cycles per thread when uops are executed in port 1
Cycles per core when uops are exectuted in port 1
Cycles per thread when uops are executed in port 2
Cycles per core when uops are dispatched to port 2
Cycles per thread when uops are executed in port 3
Cycles per core when uops are dispatched to port 3
Cycles per thread when uops are executed in port 4
Cycles per core when uops are exectuted in port 4
Cycles per thread when uops are executed in port 5
Cycles per core when uops are exectuted in port 5
Cycles per thread when uops are executed in port 6
Cycles per core when uops are exectuted in port 6
Cycles per thread when uops are executed in port 7
Cycles per core when uops are dispatched to port 7
This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads
Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.
Number of Multiply packed/scalar single precision uops allocated
Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread
Actually retired uops.
Actually retired uops.
Cycles without actually retired uops.
This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.
Retirement slots used.
Cycles without actually retired uops.
Cycles with less than 10 actually retired uops.