Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help
This section provides reference for hardware events that can be monitored for the CPU(s):
The following performance-monitoring events are supported:
Cycles the divider is busy
Divide Operations executed
Multiply operations executed
BACLEAR asserted with bad target address
BACLEAR asserted, regardless of cause
Instruction queue forced BACLEAR
Early Branch Prediciton Unit clears
Late Branch Prediction Unit clears
Branch prediction unit missed call or return
Branch instructions decoded
Branch instructions executed
Conditional branch instructions executed
Unconditional branches executed
Unconditional call branches executed
Indirect call branches executed
Indirect non call branches executed
Call branches executed
All non call branches executed
Indirect return branches executed
Taken branches executed
Retired branch instructions (Precise Event)
Retired branch instructions (Precise Event)
Retired conditional branch instructions (Precise Event)
Retired conditional branch instructions (Precise Event)
Retired near call instructions (Precise Event)
Retired near call instructions (Precise Event)
Retired near call instructions Ring 3 only(Precise Event)
Retired near call instructions Ring 3 only(Precise Event)
Mispredicted branches executed
Mispredicted conditional branches executed
Mispredicted unconditional branches executed
Mispredicted non call branches executed
Mispredicted indirect call branches executed
Mispredicted indirect non call branches executed
Mispredicted call branches executed
Mispredicted non call branches executed
Mispredicted return branches executed
Mispredicted taken branches executed
Mispredicted retired branch instructions (Precise Event)
Mispredicted retired branch instructions (Precise Event)
Mispredicted conditional retired branches (Precise Event)
Mispredicted conditional retired branches (Precise Event)
Mispredicted near retired calls (Precise Event)
Mispredicted near retired calls (Precise Event)
Cycles L1D locked
Cycles L1D and L2 locked
Reference cycles when thread is not halted (fixed counter)
Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
Cycles when thread is not halted (fixed counter)
Cycles thread is active
Total CPU cycles
DTLB load misses
DTLB load miss large page walks
DTLB load miss caused by low part of address
DTLB second level hit
DTLB load miss page walks complete
DTLB load miss page walk cycles
DTLB misses
DTLB miss large page walks
DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.
DTLB first level misses but second level hit
DTLB miss page walks
DTLB miss page walk cycles
Extended Page Table walk cycles
ES segment renames
X87 Floating point assists (Precise Event)
X87 Floating point assists (Precise Event)
X87 Floating poiint assists for invalid input value (Precise Event)
X87 Floating poiint assists for invalid input value (Precise Event)
X87 Floating point assists for invalid output value (Precise Event)
X87 Floating point assists for invalid output value (Precise Event)
MMX Uops
SSE2 integer Uops
SSE* FP double precision Uops
SSE and SSE2 FP Uops
SSE FP packed Uops
SSE FP scalar Uops
SSE* FP single precision Uops
Computational floating-point operations executed
All Floating Point to and from MMX transitions
Transitions from MMX to Floating Point instructions
Transitions from Floating Point to MMX instructions
Any Instruction Length Decoder stall cycles
Instruction Queue full stall cycles
Length Change Prefix stall cycles
Stall cycles due to BPU MRU bypass
Regen stall cycles
Instructions that must be decoded by decoder 0
Instructions written to instruction queue.
Cycles instructions are written to the instruction queue
Instructions retired (fixed counter)
Instructions retired (Programmable counter and Precise Event)
Instructions retired (Programmable counter and Precise Event)
Retired MMX instructions (Precise Event)
Retired MMX instructions (Precise Event)
Total cycles (Precise Event)
Total cycles (Precise Event)
Retired floating-point operations (Precise Event)
Retired floating-point operations (Precise Event)
I/O transactions
ITLB flushes
ITLB miss
ITLB miss large page walks
ITLB miss page walks
ITLB miss page walk cycles
Retired instructions that missed the ITLB (Precise Event)
Retired instructions that missed the ITLB (Precise Event)
L1D cache lines replaced in M state
L1D cache lines allocated in the M state
L1D snoop eviction of cache lines in M state
L1 data cache lines allocated
L1D prefetch load lock accepted in fill buffer
L1D hardware prefetch misses
L1D hardware prefetch requests
L1D hardware prefetch requests triggered
L1 writebacks to L2 in E state
L1 writebacks to L2 in I state (misses)
All L1 writebacks to L2
L1 writebacks to L2 in M state
L1 writebacks to L2 in S state
L1I instruction fetch stall cycles
L1I instruction fetch hits
L1I instruction fetch misses
L1I Instruction fetches
All L2 data requests
L2 data demand loads in E state
L2 data demand loads in I state (misses)
L2 data demand requests
L2 data demand loads in M state
L2 data demand loads in S state
L2 data prefetches in E state
L2 data prefetches in the I state (misses)
All L2 data prefetches
L2 data prefetches in M state
L2 data prefetches in the S state
L2 lines alloacated
L2 lines allocated in the E state
L2 lines allocated in the S state
L2 lines evicted
L2 lines evicted by a demand request
L2 modified lines evicted by a demand request
L2 lines evicted by a prefetch request
L2 modified lines evicted by a prefetch request
L2 instruction fetches
L2 instruction fetch hits
L2 instruction fetch misses
L2 load hits
L2 load misses
L2 requests
All L2 misses
All L2 prefetches
L2 prefetch hits
L2 prefetch misses
All L2 requests
L2 RFO requests
L2 RFO hits
L2 RFO misses
All L2 transactions
L2 fill transactions
L2 instruction fetch transactions
L1D writeback to L2 transactions
L2 Load transactions
L2 prefetch transactions
L2 RFO transactions
L2 writeback to LLC transactions
L2 demand lock RFOs in E state
All demand L2 lock RFOs that hit the cache
L2 demand lock RFOs in I state (misses)
All demand L2 lock RFOs
L2 demand lock RFOs in M state
L2 demand lock RFOs in S state
All L2 demand store RFOs that hit the cache
L2 demand store RFOs in I state (misses)
All L2 demand store RFOs
L2 demand store RFOs in M state
L2 demand store RFOs in S state
Large ITLB hit
Loads that partially overlap an earlier store
All loads dispatched
Loads dispatched from the MOB
Loads dispatched that bypass the MOB
Loads dispatched from stage 305
Load operations conflicting with software prefetches
Longest latency cache miss
Longest latency cache reference
Cycles when uops were delivered by the LSD
Cycles no uops were delivered by the LSD
Loops that can't stream from the instruction queue
Cycles machine clear asserted
Execution pipeline restart due to Memory ordering conflicts
Self-Modifying Code detected
Instructions decoded
Macro-fused instructions decoded
Memory instructions retired above 0 clocks (Precise Event)
Memory instructions retired above 1024 clocks (Precise Event)
Memory instructions retired above 128 clocks (Precise Event)
Memory instructions retired above 16 clocks (Precise Event)
Memory instructions retired above 16384 clocks (Precise Event)
Memory instructions retired above 2048 clocks (Precise Event)
Memory instructions retired above 256 clocks (Precise Event)
Memory instructions retired above 32 clocks (Precise Event)
Memory instructions retired above 32768 clocks (Precise Event)
Memory instructions retired above 4 clocks (Precise Event)
Memory instructions retired above 4096 clocks (Precise Event)
Memory instructions retired above 512 clocks (Precise Event)
Memory instructions retired above 64 clocks (Precise Event)
Memory instructions retired above 8 clocks (Precise Event)
Memory instructions retired above 8192 clocks (Precise Event)
Instructions retired which contains a load (Precise Event)
Instructions retired which contains a load (Precise Event)
Instructions retired which contains a store (Precise Event)
Instructions retired which contains a store (Precise Event)
Retired loads that miss the DTLB (Precise Event)
Retired loads that miss the DTLB (Precise Event)
Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)
Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)
Retired loads that hit the L1 data cache (Precise Event)
Retired loads that hit the L1 data cache (Precise Event)
Retired loads that hit the L2 cache (Precise Event)
Retired loads that hit the L2 cache (Precise Event)
Retired loads that miss the LLC cache (Precise Event)
Retired loads that miss the LLC cache (Precise Event)
Retired loads that hit valid versions in the LLC cache (Precise Event)
Retired loads that hit valid versions in the LLC cache (Precise Event)
Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)
Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)
Retired stores that miss the DTLB (Precise Event)
Retired stores that miss the DTLB (Precise Event)
Load instructions retired local dram and remote cache HIT data sources (Precise Event)
Load instructions retired local dram and remote cache HIT data sources (Precise Event)
Load instructions retired that HIT modified data in sibling core (Precise Event)
Load instructions retired that HIT modified data in sibling core (Precise Event)
Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)
Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)
Retired loads that hit remote socket in modified state (Precise Event)
Retired loads that hit remote socket in modified state (Precise Event)
Load instructions retired IO (Precise Event)
Load instructions retired IO (Precise Event)
Misaligned store references
All offcore requests
Offcore read requests
Offcore RFO requests
Offcore demand code read requests
Offcore demand data read requests
Offcore demand RFO requests
Offcore L1 data cache writebacks
Outstanding offcore reads
Cycles offcore reads busy
Outstanding offcore demand code reads
Cycles offcore demand code read busy
Outstanding offcore demand data reads
Cycles offcore demand data read busy
Outstanding offcore demand RFOs
Cycles offcore demand RFOs busy
Offcore requests blocked due to Super Queue full
Offcore data reads satisfied by any cache or DRAM
Offcore data reads satisfied by any DRAM
Offcore data reads that missed the LLC
All offcore data reads
Offcore data reads satisfied by the IO, CSR, MMIO unit
Offcore data reads satisfied by the LLC and not found in a sibling core
Offcore data reads satisfied by the LLC and HIT in a sibling core
Offcore data reads satisfied by the LLC and HITM in a sibling core
Offcore data reads satisfied by the LLC
Offcore data reads satisfied by the LLC or local DRAM
Offcore data reads satisfied by the local DRAM
Offcore data reads satisfied by a remote cache
Offcore data reads satisfied by a remote cache or remote DRAM
Offcore data reads that HIT in a remote cache
Offcore data reads that HITM in a remote cache
Offcore data reads satisfied by a remote DRAM
Offcore code reads satisfied by any cache or DRAM
Offcore code reads satisfied by any DRAM
Offcore code reads that missed the LLC
All offcore code reads
Offcore code reads satisfied by the IO, CSR, MMIO unit
Offcore code reads satisfied by the LLC and not found in a sibling core
Offcore code reads satisfied by the LLC and HIT in a sibling core
Offcore code reads satisfied by the LLC and HITM in a sibling core
Offcore code reads satisfied by the LLC
Offcore code reads satisfied by the LLC or local DRAM
Offcore code reads satisfied by the local DRAM
Offcore code reads satisfied by a remote cache
Offcore code reads satisfied by a remote cache or remote DRAM
Offcore code reads that HIT in a remote cache
Offcore code reads that HITM in a remote cache
Offcore code reads satisfied by a remote DRAM
Offcore requests satisfied by any cache or DRAM
Offcore requests satisfied by any DRAM
Offcore requests that missed the LLC
All offcore requests
Offcore requests satisfied by the IO, CSR, MMIO unit
Offcore requests satisfied by the LLC and not found in a sibling core
Offcore requests satisfied by the LLC and HIT in a sibling core
Offcore requests satisfied by the LLC and HITM in a sibling core
Offcore requests satisfied by the LLC
Offcore requests satisfied by the LLC or local DRAM
Offcore requests satisfied by the local DRAM
Offcore requests satisfied by a remote cache
Offcore requests satisfied by a remote cache or remote DRAM
Offcore requests that HIT in a remote cache
Offcore requests that HITM in a remote cache
Offcore requests satisfied by a remote DRAM
Offcore RFO requests satisfied by any cache or DRAM
Offcore RFO requests satisfied by any DRAM
Offcore RFO requests that missed the LLC
All offcore RFO requests
Offcore RFO requests satisfied by the IO, CSR, MMIO unit
Offcore RFO requests satisfied by the LLC and not found in a sibling core
Offcore RFO requests satisfied by the LLC and HIT in a sibling core
Offcore RFO requests satisfied by the LLC and HITM in a sibling core
Offcore RFO requests satisfied by the LLC
Offcore RFO requests satisfied by the LLC or local DRAM
Offcore RFO requests satisfied by the local DRAM
Offcore RFO requests satisfied by a remote cache
Offcore RFO requests satisfied by a remote cache or remote DRAM
Offcore RFO requests that HIT in a remote cache
Offcore RFO requests that HITM in a remote cache
Offcore RFO requests satisfied by a remote DRAM
Offcore writebacks to any cache or DRAM.
Offcore writebacks to any DRAM
Offcore writebacks that missed the LLC
All offcore writebacks
Offcore writebacks to the IO, CSR, MMIO unit.
Offcore writebacks to the LLC and not found in a sibling core
Offcore writebacks to the LLC and HITM in a sibling core
Offcore writebacks to the LLC
Offcore writebacks to the LLC or local DRAM
Offcore writebacks to the local DRAM
Offcore writebacks to a remote cache
Offcore writebacks to a remote cache or remote DRAM
Offcore writebacks that HIT in a remote cache
Offcore writebacks that HITM in a remote cache
Offcore writebacks to a remote DRAM
Offcore code or data read requests satisfied by any cache or DRAM.
Offcore code or data read requests satisfied by any DRAM
Offcore code or data read requests that missed the LLC
All offcore code or data read requests
Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.
Offcore code or data read requests satisfied by the LLC and not found in a sibling core
Offcore code or data read requests satisfied by the LLC and HIT in a sibling core
Offcore code or data read requests satisfied by the LLC and HITM in a sibling core
Offcore code or data read requests satisfied by the LLC
Offcore code or data read requests satisfied by the LLC or local DRAM
Offcore code or data read requests satisfied by the local DRAM
Offcore code or data read requests satisfied by a remote cache
Offcore code or data read requests satisfied by a remote cache or remote DRAM
Offcore code or data read requests that HIT in a remote cache
Offcore code or data read requests that HITM in a remote cache
Offcore code or data read requests satisfied by a remote DRAM
Offcore request = all data, response = any cache_dram
Offcore request = all data, response = any DRAM
Offcore request = all data, response = any LLC miss
Offcore request = all data, response = any location
Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit
Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core
Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core
Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core
Offcore request = all data, response = local cache
Offcore request = all data, response = local cache or dram
Offcore data reads, RFO's and prefetches statisfied by the local DRAM.
Offcore request = all data, response = remote cache
Offcore request = all data, response = remote cache or dram
Offcore data reads, RFO's and prefetches that HIT in a remote cache
Offcore data reads, RFO's and prefetches that HITM in a remote cache
Offcore data reads, RFO's and prefetches statisfied by the remote DRAM
Offcore demand data requests satisfied by any cache or DRAM
Offcore demand data requests satisfied by any DRAM
Offcore demand data requests that missed the LLC
All offcore demand data requests
Offcore demand data requests satisfied by the IO, CSR, MMIO unit.
Offcore demand data requests satisfied by the LLC and not found in a sibling core
Offcore demand data requests satisfied by the LLC and HIT in a sibling core
Offcore demand data requests satisfied by the LLC and HITM in a sibling core
Offcore demand data requests satisfied by the LLC
Offcore demand data requests satisfied by the LLC or local DRAM
Offcore demand data requests satisfied by the local DRAM
Offcore demand data requests satisfied by a remote cache
Offcore demand data requests satisfied by a remote cache or remote DRAM
Offcore demand data requests that HIT in a remote cache
Offcore demand data requests that HITM in a remote cache
Offcore demand data requests satisfied by a remote DRAM
Offcore demand data reads satisfied by any cache or DRAM.
Offcore demand data reads satisfied by any DRAM
Offcore demand data reads that missed the LLC
All offcore demand data reads
Offcore demand data reads satisfied by the IO, CSR, MMIO unit
Offcore demand data reads satisfied by the LLC and not found in a sibling core
Offcore demand data reads satisfied by the LLC and HIT in a sibling core
Offcore demand data reads satisfied by the LLC and HITM in a sibling core
Offcore demand data reads satisfied by the LLC
Offcore demand data reads satisfied by the LLC or local DRAM
Offcore demand data reads satisfied by the local DRAM
Offcore demand data reads satisfied by a remote cache
Offcore demand data reads satisfied by a remote cache or remote DRAM
Offcore demand data reads that HIT in a remote cache
Offcore demand data reads that HITM in a remote cache
Offcore demand data reads satisfied by a remote DRAM
Offcore demand code reads satisfied by any cache or DRAM.
Offcore demand code reads satisfied by any DRAM
Offcore demand code reads that missed the LLC
All offcore demand code reads
Offcore demand code reads satisfied by the IO, CSR, MMIO unit
Offcore demand code reads satisfied by the LLC and not found in a sibling core
Offcore demand code reads satisfied by the LLC and HIT in a sibling core
Offcore demand code reads satisfied by the LLC and HITM in a sibling core
Offcore demand code reads satisfied by the LLC
Offcore demand code reads satisfied by the LLC or local DRAM
Offcore demand code reads satisfied by the local DRAM
Offcore demand code reads satisfied by a remote cache
Offcore demand code reads satisfied by a remote cache or remote DRAM
Offcore demand code reads that HIT in a remote cache
Offcore demand code reads that HITM in a remote cache
Offcore demand code reads satisfied by a remote DRAM
Offcore demand RFO requests satisfied by any cache or DRAM.
Offcore demand RFO requests satisfied by any DRAM
Offcore demand RFO requests that missed the LLC
All offcore demand RFO requests
Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit
Offcore demand RFO requests satisfied by the LLC and not found in a sibling core
Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core
Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core
Offcore demand RFO requests satisfied by the LLC
Offcore demand RFO requests satisfied by the LLC or local DRAM
Offcore demand RFO requests satisfied by the local DRAM
Offcore demand RFO requests satisfied by a remote cache
Offcore demand RFO requests satisfied by a remote cache or remote DRAM
Offcore demand RFO requests that HIT in a remote cache
Offcore demand RFO requests that HITM in a remote cache
Offcore demand RFO requests satisfied by a remote DRAM
Offcore other requests satisfied by any cache or DRAM.
Offcore other requests satisfied by any DRAM
Offcore other requests that missed the LLC
All offcore other requests
Offcore other requests satisfied by the IO, CSR, MMIO unit
Offcore other requests satisfied by the LLC and not found in a sibling core
Offcore other requests satisfied by the LLC and HIT in a sibling core
Offcore other requests satisfied by the LLC and HITM in a sibling core
Offcore other requests satisfied by the LLC
Offcore other requests satisfied by the LLC or local DRAM
Offcore other requests satisfied by a remote cache
Offcore other requests satisfied by a remote cache or remote DRAM
Offcore other requests that HIT in a remote cache
Offcore other requests that HITM in a remote cache
Offcore other requests satisfied by a remote DRAM
Offcore prefetch data requests satisfied by any cache or DRAM
Offcore prefetch data requests satisfied by any DRAM
Offcore prefetch data requests that missed the LLC
All offcore prefetch data requests
Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.
Offcore prefetch data requests satisfied by the LLC and not found in a sibling core
Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core
Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core
Offcore prefetch data requests satisfied by the LLC
Offcore prefetch data requests satisfied by the LLC or local DRAM
Offcore prefetch data requests satisfied by the local DRAM
Offcore prefetch data requests satisfied by a remote cache
Offcore prefetch data requests satisfied by a remote cache or remote DRAM
Offcore prefetch data requests that HIT in a remote cache
Offcore prefetch data requests that HITM in a remote cache
Offcore prefetch data requests satisfied by a remote DRAM
Offcore prefetch data reads satisfied by any cache or DRAM.
Offcore prefetch data reads satisfied by any DRAM
Offcore prefetch data reads that missed the LLC
All offcore prefetch data reads
Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit
Offcore prefetch data reads satisfied by the LLC and not found in a sibling core
Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core
Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core
Offcore prefetch data reads satisfied by the LLC
Offcore prefetch data reads satisfied by the LLC or local DRAM
Offcore prefetch data reads satisfied by the local DRAM
Offcore prefetch data reads satisfied by a remote cache
Offcore prefetch data reads satisfied by a remote cache or remote DRAM
Offcore prefetch data reads that HIT in a remote cache
Offcore prefetch data reads that HITM in a remote cache
Offcore prefetch data reads satisfied by a remote DRAM
Offcore prefetch code reads satisfied by any cache or DRAM.
Offcore prefetch code reads satisfied by any DRAM
Offcore prefetch code reads that missed the LLC
All offcore prefetch code reads
Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit
Offcore prefetch code reads satisfied by the LLC and not found in a sibling core
Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core
Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core
Offcore prefetch code reads satisfied by the LLC
Offcore prefetch code reads satisfied by the LLC or local DRAM
Offcore prefetch code reads satisfied by the local DRAM
Offcore prefetch code reads satisfied by a remote cache
Offcore prefetch code reads satisfied by a remote cache or remote DRAM
Offcore prefetch code reads that HIT in a remote cache
Offcore prefetch code reads that HITM in a remote cache
Offcore prefetch code reads satisfied by a remote DRAM
Offcore prefetch RFO requests satisfied by any cache or DRAM.
Offcore prefetch RFO requests satisfied by any DRAM
Offcore prefetch RFO requests that missed the LLC
All offcore prefetch RFO requests
Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit
Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core
Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core
Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core
Offcore prefetch RFO requests satisfied by the LLC
Offcore prefetch RFO requests satisfied by the LLC or local DRAM
Offcore prefetch RFO requests satisfied by the local DRAM
Offcore prefetch RFO requests satisfied by a remote cache
Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM
Offcore prefetch RFO requests that HIT in a remote cache
Offcore prefetch RFO requests that HITM in a remote cache
Offcore prefetch RFO requests satisfied by a remote DRAM
Offcore prefetch requests satisfied by any cache or DRAM.
Offcore prefetch requests satisfied by any DRAM
Offcore prefetch requests that missed the LLC
All offcore prefetch requests
Offcore prefetch requests satisfied by the IO, CSR, MMIO unit
Offcore prefetch requests satisfied by the LLC and not found in a sibling core
Offcore prefetch requests satisfied by the LLC and HIT in a sibling core
Offcore prefetch requests satisfied by the LLC and HITM in a sibling core
Offcore prefetch requests satisfied by the LLC
Offcore prefetch requests satisfied by the LLC or local DRAM
Offcore prefetch requests satisfied by the local DRAM
Offcore prefetch requests satisfied by a remote cache
Offcore prefetch requests satisfied by a remote cache or remote DRAM
Offcore prefetch requests that HIT in a remote cache
Offcore prefetch requests that HITM in a remote cache
Offcore prefetch requests satisfied by a remote DRAM
False dependencies due to partial address aliasing
All RAT stall cycles
Flag stall cycles
Partial register stall cycles
ROB read port stalls cycles
Scoreboard stall cycles
Resource related stall cycles
FPU control word write stall cycles
Load buffer stall cycles
MXCSR rename stall cycles
Other Resource related stall cycles
ROB full stall cycles
Reservation Station full stall cycles
Store buffer stall cycles
All Store buffer stall cycles
Segment rename stall cycles
128 bit SIMD integer pack operations
128 bit SIMD integer arithmetic operations
128 bit SIMD integer logical operations
128 bit SIMD integer multiply operations
128 bit SIMD integer shift operations
128 bit SIMD integer shuffle/move operations
128 bit SIMD integer unpack operations
SIMD integer 64 bit pack operations
SIMD integer 64 bit arithmetic operations
SIMD integer 64 bit logical operations
SIMD integer 64 bit packed multiply operations
SIMD integer 64 bit shift operations
SIMD integer 64 bit shuffle/move operations
SIMD integer 64 bit unpack operations
Snoop code requests
Snoop data requests
Snoop invalidate requests
Outstanding snoop code requests
Cycles snoop code requests queued
Outstanding snoop data requests
Cycles snoop data requests queued
Outstanding snoop invalidate requests
Cycles snoop invalidate requests queued
Thread responded HIT to snoop
Thread responded HITE to snoop
Thread responded HITM to snoop
Super Queue full stall cycles
Super Queue LRU hints sent to LLC
Super Queue lock splits across a cache line
SIMD Packed-Double Uops retired (Precise Event)
SIMD Packed-Double Uops retired (Precise Event)
SIMD Packed-Single Uops retired (Precise Event)
SIMD Packed-Single Uops retired (Precise Event)
SIMD Scalar-Double Uops retired (Precise Event)
SIMD Scalar-Double Uops retired (Precise Event)
SIMD Scalar-Single Uops retired (Precise Event)
SIMD Scalar-Single Uops retired (Precise Event)
SIMD Vector Integer Uops retired (Precise Event)
SIMD Vector Integer Uops retired (Precise Event)
Loads delayed with at-Retirement block code
Cacheable loads delayed with L1D block code
Two Uop instructions decoded
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Counts Output port sends NULL flit
ANY Data Response Messages
Counts Output port sends NULL flit
Times target available at output port
uncore clock frequency
Stack pointer instructions decoded
Stack pointer sync operations
Uops decoded by Microcode Sequencer
Cycles no Uops are decoded
Cycles Uops executed on any port (core count)
Cycles Uops executed on ports 0-4 (core count)
Uops executed on any port (core count)
Uops executed on ports 0-4 (core count)
Cycles no Uops issued on any port (core count)
Cycles no Uops issued on ports 0-4 (core count)
Uops executed on port 0
Uops issued on ports 0, 1 or 5
Cycles no Uops issued on ports 0, 1 or 5
Uops executed on port 1
Uops issued on ports 2, 3 or 4
Uops executed on port 2 (core count)
Uops executed on port 3 (core count)
Uops executed on port 4 (core count)
Uops executed on port 5
Uops issued
Cycles no Uops were issued on any thread
Cycles Uops were issued on either thread
Fused Uops issued
Cycles no Uops were issued
Cycles Uops are being retired
Cycles Uops are being retired
Uops retired (Precise Event)
Uops retired (Precise Event)
Macro-fused Uops retired (Precise Event)
Macro-fused Uops retired (Precise Event)
Retirement slots used (Precise Event)
Retirement slots used (Precise Event)
Cycles Uops are not retiring (Precise Event)
Cycles Uops are not retiring (Precise Event)
Total cycles using precise uop retired event (Precise Event)
Total cycles using precise uop retired event (Precise Event)
Uop unfusions due to FP exceptions