Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help

Events for Intel® Microarchitecture Code Name Skylake

This section provides reference for hardware events that can be monitored for the CPU(s):

The following performance-monitoring events are supported:

ARITH.DIVIDER_ACTIVE

Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.

BACLEARS.ANY

Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.

BR_INST_RETIRED.ALL_BRANCHES

This event counts all (macro) branch instructions retired.

BR_INST_RETIRED.ALL_BRANCHES_PS

This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.

BR_INST_RETIRED.CONDITIONAL

This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.

BR_INST_RETIRED.CONDITIONAL_PS

This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.

BR_INST_RETIRED.FAR_BRANCH

This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.

BR_INST_RETIRED.FAR_BRANCH_PS

This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired.

BR_INST_RETIRED.NEAR_CALL

This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.

BR_INST_RETIRED.NEAR_CALL_PS

This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.

BR_INST_RETIRED.NEAR_RETURN

This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.

BR_INST_RETIRED.NEAR_RETURN_PS

This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.

BR_INST_RETIRED.NEAR_TAKEN

This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.

BR_INST_RETIRED.NEAR_TAKEN_PS

This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.

BR_INST_RETIRED.NOT_TAKEN

This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.

BR_MISP_RETIRED.ALL_BRANCHES

This event counts all mispredicted macro branch instructions retired.

BR_MISP_RETIRED.ALL_BRANCHES_PS

This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.

BR_MISP_RETIRED.CONDITIONAL

This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.

BR_MISP_RETIRED.CONDITIONAL_PS

This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.

BR_MISP_RETIRED.NEAR_TAKEN

number of near branch instructions retired that were mispredicted and taken.

BR_MISP_RETIRED.NEAR_TAKEN_PS

number of near branch instructions retired that were mispredicted and taken.

CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE

Count XClk pulses when this thread is unhalted and the other thread is halted.

CPU_CLK_THREAD_UNHALTED.REF_XCLK

Reference cycles when the thread is unhalted (counts at 100 MHz rate)

CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY

Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)

CPU_CLK_UNHALTED.REF_TSC

This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling ™' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case

CPU_CLK_UNHALTED.THREAD

This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events

CPU_CLK_UNHALTED.THREAD_ANY

Core cycles when at least one thread on the physical core is not in halt state

CPU_CLK_UNHALTED.THREAD_P

This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.

CPU_CLK_UNHALTED.THREAD_P_ANY

Core cycles when at least one thread on the physical core is not in halt state

CYCLE_ACTIVITY.CYCLES_L1D_MISS

Cycles while L1 cache miss demand load is outstanding.

CYCLE_ACTIVITY.CYCLES_L2_MISS

Cycles while L2 cache miss demand load is outstanding.

CYCLE_ACTIVITY.CYCLES_L3_MISS

Cycles while L3 cache miss demand load is outstanding.

CYCLE_ACTIVITY.CYCLES_MEM_ANY

Cycles while memory subsystem has an outstanding load.

CYCLE_ACTIVITY.STALLS_L1D_MISS

Execution stalls while L1 cache miss demand load is outstanding.

CYCLE_ACTIVITY.STALLS_L2_MISS

Execution stalls while L2 cache miss demand load is outstanding.

CYCLE_ACTIVITY.STALLS_L3_MISS

Execution stalls while L3 cache miss demand load is outstanding.

CYCLE_ACTIVITY.STALLS_MEM_ANY

Execution stalls while memory subsystem has an outstanding load.

CYCLE_ACTIVITY.STALLS_TOTAL

Total execution stalls.

DSB2MITE_SWITCHES.PENALTY_CYCLES

This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.

DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK

This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

DTLB_LOAD_MISSES.STLB_HIT

Loads that miss the DTLB and hit the STLB.

DTLB_LOAD_MISSES.WALK_ACTIVE

Cycles when at least one PMH is busy with a page walk for a load.

DTLB_LOAD_MISSES.WALK_COMPLETED

Load miss in all TLB levels causes a page walk that completes. (All page sizes)

DTLB_LOAD_MISSES.WALK_PENDING

Counts 1 per cycle for each PMH that is busy with a page walk for a load.

DTLB_STORE_MISSES.MISS_CAUSES_A_WALK

This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

DTLB_STORE_MISSES.STLB_HIT

Stores that miss the DTLB and hit the STLB.

DTLB_STORE_MISSES.WALK_ACTIVE

Cycles when at least one PMH is busy with a page walk for a store.

DTLB_STORE_MISSES.WALK_COMPLETED

Store misses in all TLB levels causes a page walk that completes. (All page sizes)

DTLB_STORE_MISSES.WALK_PENDING

Counts 1 per cycle for each PMH that is busy with a page walk for a store.

EPT.WALK_PENDING

Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.

EXE_ACTIVITY.1_PORTS_UTIL

Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.

EXE_ACTIVITY.2_PORTS_UTIL

Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.

EXE_ACTIVITY.3_PORTS_UTIL

Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.

EXE_ACTIVITY.4_PORTS_UTIL

Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.

EXE_ACTIVITY.BOUND_ON_STORES

Cycles where the Store Buffer was full and no outstanding load.

EXE_ACTIVITY.EXE_BOUND_0_PORTS

Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.

FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE

Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE

Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE

Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE

Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.SCALAR_DOUBLE

Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.SCALAR_SINGLE

Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ASSIST.ANY

This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.

FRONTEND_RETIRED.DSB_MISS

Retired Instructions who experienced decode stream buffer (DSB - the decoded insturction-cache) miss.

FRONTEND_RETIRED.DSB_MISS_PS

Retired Instructions who experienced decode stream buffer (DSB - the decoded insturction-cache) miss. Precise Event.

FRONTEND_RETIRED.ITLB_MISS

Retired Instructions who experienced iTLB true miss.

FRONTEND_RETIRED.ITLB_MISS_PS

Retired Instructions who experienced iTLB true miss. Precise Event.

FRONTEND_RETIRED.L1I_MISS

Retired Instructions who experienced Instruction L1 Cache true miss.

FRONTEND_RETIRED.L1I_MISS_PS

Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event.

FRONTEND_RETIRED.L2_MISS

Retired Instructions who experienced Instruction L2 Cache true miss.

FRONTEND_RETIRED.L2_MISS_PS

Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_128

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_128_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_16

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_16_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_2

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_256

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall

FRONTEND_RETIRED.LATENCY_GE_256_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1

Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS

Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2

Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2_PS

Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3

Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3_PS

Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_2_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_32

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_32_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_4

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_4_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_512

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_512_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event.

FRONTEND_RETIRED.LATENCY_GE_64

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_64_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event

FRONTEND_RETIRED.LATENCY_GE_8

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.LATENCY_GE_8_PS

Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.

FRONTEND_RETIRED.STLB_MISS

Retired Instructions who experienced STLB (2nd level TLB) true miss.

FRONTEND_RETIRED.STLB_MISS_PS

Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event.

HLE_RETIRED.ABORTED

Number of times HLE abort was triggered

HLE_RETIRED.ABORTED_EVENTS

Number of times an HLE execution aborted due to unfriendly events (such as interrupts).

HLE_RETIRED.ABORTED_MEM

Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).

HLE_RETIRED.ABORTED_MEMTYPE

Number of times an HLE execution aborted due to incompatible memory type

HLE_RETIRED.ABORTED_PS

Number of times HLE abort was triggered (PEBS)

HLE_RETIRED.ABORTED_TIMER

Number of times an HLE execution aborted due to hardware timer expiration.

HLE_RETIRED.ABORTED_UNFRIENDLY

Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).

HLE_RETIRED.COMMIT

Number of times HLE commit succeeded

HLE_RETIRED.START

Number of times we entered an HLE region does not count nested transactions

HW_INTERRUPTS.RECEIVED

This event counts the number of hardware interruptions received by the processor.

ICACHE_16B.IFDATA_STALL

Cycles where a code fetch is stalled due to L1 instruction cache miss.

ICACHE_64B.IFTAG_HIT

Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.

ICACHE_64B.IFTAG_MISS

Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.

ICACHE_64B.IFTAG_STALL

Cycles where a code fetch is stalled due to L1 instruction cache tag miss.

IDQ.ALL_DSB_CYCLES_4_UOPS

This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.

IDQ.ALL_DSB_CYCLES_ANY_UOPS

This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.

IDQ.ALL_MITE_CYCLES_4_UOPS

This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).

IDQ.ALL_MITE_CYCLES_ANY_UOPS

This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).

IDQ.DSB_CYCLES

This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.

IDQ.DSB_UOPS

This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.

IDQ.MITE_CYCLES

This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.

IDQ.MITE_UOPS

This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).

IDQ.MS_CYCLES

This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.

IDQ.MS_DSB_CYCLES

This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.

IDQ.MS_MITE_UOPS

This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may 'bypass' the IDQ.

IDQ.MS_SWITCHES

Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer

IDQ.MS_UOPS

This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.

IDQ_UOPS_NOT_DELIVERED.CORE

This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions) c. Instruction Decode Queue (IDQ) delivers four uops.

IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE

This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.

IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK

Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE

This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE

Cycles with less than 2 uops delivered by the front end

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE

Cycles with less than 3 uops delivered by the front end

ILD_STALL.LCP

This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.

INST_RETIRED.ANY

This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions

INST_RETIRED.ANY_P

This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).

INST_RETIRED.PREC_DIST

This is a precise version (that is, uses PEBS) of the event that counts instructions retired.

INST_RETIRED.TOTAL_CYCLES_PS

Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16)

INT_MISC.CLEAR_RESTEER_CYCLES

Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.

INT_MISC.RECOVERY_CYCLES

Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear

INT_MISC.RECOVERY_CYCLES_ANY

Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)

ITLB.ITLB_FLUSH

This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).

ITLB_MISSES.MISS_CAUSES_A_WALK

This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

ITLB_MISSES.STLB_HIT

Intruction fetch requests that miss the ITLB and hit the STLB.

ITLB_MISSES.WALK_COMPLETED

Code miss in all TLB levels causes a page walk that completes. (All page sizes)

ITLB_MISSES.WALK_PENDING

Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request.

L1D.REPLACEMENT

This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.

L1D_PEND_MISS.FB_FULL

Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e

L1D_PEND_MISS.PENDING

This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.

L1D_PEND_MISS.PENDING_CYCLES

This event counts duration of L1D miss outstanding in cycles.

L1D_PEND_MISS.PENDING_CYCLES_ANY

Cycles with L1D load Misses outstanding from any thread on physical core

L2_LINES_IN.ALL

This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.

L2_LINES_OUT.NON_SILENT

tbd

L2_LINES_OUT.SILENT

tbd

L2_LINES_OUT.USELESS_PREF

tbd

L2_RQSTS.ALL_CODE_RD

This event counts the total number of L2 code requests.

L2_RQSTS.ALL_DEMAND_DATA_RD

This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.

L2_RQSTS.ALL_DEMAND_MISS

Demand requests that miss L2 cache

L2_RQSTS.ALL_DEMAND_REFERENCES

Demand requests to L2 cache

L2_RQSTS.ALL_PF

This event counts the total number of requests from the L2 hardware prefetchers.

L2_RQSTS.ALL_RFO

This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.

L2_RQSTS.CODE_RD_HIT

L2 cache hits when fetching instructions, code reads.

L2_RQSTS.CODE_RD_MISS

L2 cache misses when fetching instructions

L2_RQSTS.DEMAND_DATA_RD_HIT

This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.

L2_RQSTS.DEMAND_DATA_RD_MISS

This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.

L2_RQSTS.MISS

All requests that miss L2 cache

L2_RQSTS.PF_HIT

Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache

L2_RQSTS.PF_MISS

Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache

L2_RQSTS.REFERENCES

All L2 requests

L2_RQSTS.RFO_HIT

RFO requests that hit L2 cache

L2_RQSTS.RFO_MISS

RFO requests that miss L2 cache

L2_TRANS.L2_WB

This event counts L2 writebacks that access L2 cache.

LD_BLOCKS.NO_SR

The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use

LD_BLOCKS.STORE_FORWARD

This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: - preceding store conflicts with the load (incomplete overlap) - store forwarding is impossible due to u-arch limitations - preceding lock RMW operations are not forwarded - store has the no-forward bit set (uncacheable/page-split/masked stores) - all-blocking stores are used (mostly, fences and port I/O) and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide.

LD_BLOCKS_PARTIAL.ADDRESS_ALIAS

This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.

LOAD_HIT_PRE.SW_PF

This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.

LOCK_CYCLES.CACHE_LOCK_DURATION

This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).

LONGEST_LAT_CACHE.MISS

This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.

LONGEST_LAT_CACHE.REFERENCE

This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.

LSD.CYCLES_4_UOPS

Cycles 4 Uops delivered by the LSD, but didn't come from the decoder

LSD.CYCLES_ACTIVE

Cycles Uops delivered by the LSD, but didn't come from the decoder

LSD.UOPS

Number of Uops delivered by the LSD.

MACHINE_CLEARS.COUNT

Number of machine clears (nukes) of any type.

MACHINE_CLEARS.MEMORY_ORDERING

This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer.

MACHINE_CLEARS.SMC

This event counts self-modifying code (SMC) detected, which causes a machine clear.

MEM_INST_RETIRED.ALL_LOADS

All retired load instructions.

MEM_INST_RETIRED.ALL_LOADS_PS

All retired load instructions. (Precise Event)

MEM_INST_RETIRED.ALL_STORES

All retired store instructions.

MEM_INST_RETIRED.ALL_STORES_PS

All retired store instructions. (Precise Event)

MEM_INST_RETIRED.LOCK_LOADS

Retired load instructions with locked access.

MEM_INST_RETIRED.LOCK_LOADS_PS

Retired load instructions with locked access. (Precise Event)

MEM_INST_RETIRED.SPLIT_LOADS

Retired load instructions that split across a cacheline boundary.

MEM_INST_RETIRED.SPLIT_LOADS_PS

Retired load instructions that split across a cacheline boundary. (Precise Event)

MEM_INST_RETIRED.SPLIT_STORES

Retired store instructions that split across a cacheline boundary.

MEM_INST_RETIRED.SPLIT_STORES_PS

Retired store instructions that split across a cacheline boundary. (Precise Event)

MEM_INST_RETIRED.STLB_MISS_LOADS

Retired load instructions that miss the STLB.

MEM_INST_RETIRED.STLB_MISS_LOADS_PS

Retired load instructions that miss the STLB. (Precise Event)

MEM_INST_RETIRED.STLB_MISS_STORES

Retired store instructions that miss the STLB.

MEM_INST_RETIRED.STLB_MISS_STORES_PS

Retired store instructions that miss the STLB. (Precise Event)

MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT

Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache

MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM

Retired load instructions which data sources were HitM responses from shared L3

MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS

Retired load instructions which data sources were HitM responses from shared L3

MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS

Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache

MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS

Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.

MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS

Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.

MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE

Retired load instructions which data sources were hits in L3 without snoops required

MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE_PS

Retired load instructions which data sources were hits in L3 without snoops required

MEM_LOAD_RETIRED.FB_HIT

Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready

MEM_LOAD_RETIRED.FB_HIT_PS

Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready

MEM_LOAD_RETIRED.L1_HIT

Retired load instructions with L1 cache hits as data sources

MEM_LOAD_RETIRED.L1_HIT_PS

Retired load instructions with L1 cache hits as data sources

MEM_LOAD_RETIRED.L1_MISS

Retired load instructions missed L1 cache as data sources

MEM_LOAD_RETIRED.L1_MISS_PS

Retired load instructions missed L1 cache as data sources

MEM_LOAD_RETIRED.L2_HIT

Retired load instructions with L2 cache hits as data sources

MEM_LOAD_RETIRED.L2_HIT_PS

Retired load instructions with L2 cache hits as data sources

MEM_LOAD_RETIRED.L2_MISS

Retired load instructions missed L2 cache as data sources

MEM_LOAD_RETIRED.L2_MISS_PS

Retired load instructions missed L2 cache as data sources

MEM_LOAD_RETIRED.L3_HIT

Retired load instructions with L3 cache hits as data sources

MEM_LOAD_RETIRED.L3_HIT_PS

Retired load instructions with L3 cache hits as data sources

MEM_LOAD_RETIRED.L3_MISS

Retired load instructions missed L3 cache as data sources

MEM_LOAD_RETIRED.L3_MISS_PS

Retired load instructions missed L3 cache as data sources

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128

Counts loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16

Counts loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256

Counts loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32

Counts loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4

Counts loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512

Counts loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64

Counts loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8

Counts loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.

OFFCORE_REQUESTS.ALL_DATA_RD

This event counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.

OFFCORE_REQUESTS.ALL_REQUESTS

This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.

OFFCORE_REQUESTS.DEMAND_CODE_RD

This event counts both cacheable and noncachaeble code read requests.

OFFCORE_REQUESTS.DEMAND_DATA_RD

This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.

OFFCORE_REQUESTS.DEMAND_RFO

This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.

OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD

Demand Data Read requests who miss L3 cache

OFFCORE_REQUESTS_BUFFER.SQ_FULL

This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full. Note: Writeback pending FIFO has six entries.

OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD

This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD

This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD

This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD

This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO

This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD

Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD

This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD

This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS. Note: A prefetch promoted to Demand is counted from the promotion point.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6

Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO

This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD

Counts number of Offcore outstanding Demand Data Read requests who miss L3 cache in the superQ every cycle.

OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6

Cycles with at least 6 Demand Data Read requests who miss L3 cache in the superQ

OFFCORE_RESPONSE

Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=ANY_RESPONSE

Counts all demand code reads that have any response type.

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.ANY_SNOOP

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_HITM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_HIT_NO_FWD

Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_MISS

Counts all demand code reads that hit in the L3 and the snoops sent to sibling cores return clean response.

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_NONE

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_NON_DRAM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SNOOP_NOT_NEEDED

Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT.SPL_HIT

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.ANY_SNOOP

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SNOOP_HITM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SNOOP_HIT_NO_FWD

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SNOOP_MISS

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SNOOP_NONE

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SNOOP_NON_DRAM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SNOOP_NOT_NEEDED

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_E.SPL_HIT

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.ANY_SNOOP

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SNOOP_HITM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SNOOP_HIT_NO_FWD

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SNOOP_MISS

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SNOOP_NONE

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SNOOP_NON_DRAM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SNOOP_NOT_NEEDED

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_M.SPL_HIT

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.ANY_SNOOP

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SNOOP_HITM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SNOOP_HIT_NO_FWD

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SNOOP_MISS

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SNOOP_NONE

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SNOOP_NON_DRAM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SNOOP_NOT_NEEDED

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_HIT_S.SPL_HIT

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.ANY_SNOOP

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_HITM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_HIT_NO_FWD

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_MISS

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_NONE

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_NON_DRAM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_NOT_NEEDED

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SPL_HIT

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_HITM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SPL_HIT

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.ANY_SNOOP

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.SNOOP_HITM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.SNOOP_HIT_WITH_FWD

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.SNOOP_MISS

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.SNOOP_NONE

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.SNOOP_NON_DRAM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L4_HIT_LOCAL_L4.SPL_HIT

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.ANY_SNOOP

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SNOOP_HITM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SNOOP_MISS

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SNOOP_NONE

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SNOOP_NON_DRAM

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SNOOP_NOT_NEEDED

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=SUPPLIER_NONE.SPL_HIT

Counts all demand code reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=ANY_RESPONSE

Counts demand data reads that have any response type.

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.ANY_SNOOP

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_HITM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_HIT_NO_FWD

Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_MISS

Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response.

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_NONE

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_NON_DRAM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SNOOP_NOT_NEEDED

Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT.SPL_HIT

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.ANY_SNOOP

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SNOOP_HITM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SNOOP_HIT_NO_FWD

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SNOOP_MISS

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SNOOP_NONE

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SNOOP_NON_DRAM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SNOOP_NOT_NEEDED

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_E.SPL_HIT

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.ANY_SNOOP

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SNOOP_HITM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SNOOP_HIT_NO_FWD

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SNOOP_MISS

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SNOOP_NONE

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SNOOP_NON_DRAM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SNOOP_NOT_NEEDED

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_M.SPL_HIT

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.ANY_SNOOP

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SNOOP_HITM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SNOOP_HIT_NO_FWD

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SNOOP_MISS

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SNOOP_NONE

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SNOOP_NON_DRAM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SNOOP_NOT_NEEDED

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_HIT_S.SPL_HIT

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.ANY_SNOOP

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_HITM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_HIT_NO_FWD

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_MISS

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_NONE

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_NON_DRAM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_NOT_NEEDED

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SPL_HIT

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_HITM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SPL_HIT

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.ANY_SNOOP

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.SNOOP_HITM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.SNOOP_HIT_WITH_FWD

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.SNOOP_MISS

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.SNOOP_NONE

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.SNOOP_NON_DRAM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L4_HIT_LOCAL_L4.SPL_HIT

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.ANY_SNOOP

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SNOOP_HITM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SNOOP_MISS

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SNOOP_NONE

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SNOOP_NON_DRAM

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SNOOP_NOT_NEEDED

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=SUPPLIER_NONE.SPL_HIT

Counts demand data reads that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=ANY_RESPONSE

Counts all demand data writes (RFOs) that have any response type.

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.ANY_SNOOP

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_HITM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_HIT_NO_FWD

Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_MISS

Counts all demand data writes (RFOs) that hit in the L3 and the snoops sent to sibling cores return clean response.

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_NONE

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_NON_DRAM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SNOOP_NOT_NEEDED

Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT.SPL_HIT

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.ANY_SNOOP

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SNOOP_HITM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SNOOP_HIT_NO_FWD

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SNOOP_MISS

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SNOOP_NONE

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SNOOP_NON_DRAM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SNOOP_NOT_NEEDED

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_E.SPL_HIT

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.ANY_SNOOP

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SNOOP_HITM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SNOOP_HIT_NO_FWD

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SNOOP_MISS

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SNOOP_NONE

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SNOOP_NON_DRAM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SNOOP_NOT_NEEDED

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_M.SPL_HIT

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.ANY_SNOOP

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SNOOP_HITM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SNOOP_HIT_NO_FWD

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SNOOP_MISS

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SNOOP_NONE

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SNOOP_NON_DRAM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SNOOP_NOT_NEEDED

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_HIT_S.SPL_HIT

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.ANY_SNOOP

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_HITM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_HIT_NO_FWD

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_MISS

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_NONE

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_NON_DRAM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_NOT_NEEDED

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SPL_HIT

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_HITM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SPL_HIT

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.ANY_SNOOP

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.SNOOP_HITM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.SNOOP_HIT_WITH_FWD

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.SNOOP_MISS

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.SNOOP_NONE

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.SNOOP_NON_DRAM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=L4_HIT_LOCAL_L4.SPL_HIT

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.ANY_SNOOP

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SNOOP_HITM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SNOOP_MISS

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SNOOP_NONE

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SNOOP_NON_DRAM

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SNOOP_NOT_NEEDED

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=DEMAND_RFO:response=SUPPLIER_NONE.SPL_HIT

Counts all demand data writes (RFOs) that tbd

OFFCORE_RESPONSE:request=OTHER:response=ANY_RESPONSE

Counts any other requests that have any response type.

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.ANY_SNOOP

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_HITM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_HIT_NO_FWD

Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_MISS

Counts any other requests that hit in the L3 and the snoops sent to sibling cores return clean response.

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_NONE

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_NON_DRAM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SNOOP_NOT_NEEDED

Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT.SPL_HIT

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.ANY_SNOOP

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SNOOP_HITM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SNOOP_HIT_NO_FWD

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SNOOP_MISS

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SNOOP_NONE

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SNOOP_NON_DRAM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SNOOP_NOT_NEEDED

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_E.SPL_HIT

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.ANY_SNOOP

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SNOOP_HITM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SNOOP_HIT_NO_FWD

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SNOOP_MISS

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SNOOP_NONE

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SNOOP_NON_DRAM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SNOOP_NOT_NEEDED

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_M.SPL_HIT

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.ANY_SNOOP

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SNOOP_HITM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SNOOP_HIT_NO_FWD

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SNOOP_MISS

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SNOOP_NONE

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SNOOP_NON_DRAM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SNOOP_NOT_NEEDED

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_HIT_S.SPL_HIT

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.ANY_SNOOP

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_HITM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_HIT_NO_FWD

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_MISS

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_NONE

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_NON_DRAM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_NOT_NEEDED

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SPL_HIT

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_HITM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SPL_HIT

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.ANY_SNOOP

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.SNOOP_HITM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.SNOOP_HIT_WITH_FWD

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.SNOOP_MISS

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.SNOOP_NONE

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.SNOOP_NON_DRAM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=L4_HIT_LOCAL_L4.SPL_HIT

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.ANY_SNOOP

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SNOOP_HITM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SNOOP_MISS

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SNOOP_NONE

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SNOOP_NON_DRAM

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SNOOP_NOT_NEEDED

Counts any other requests that tbd

OFFCORE_RESPONSE:request=OTHER:response=SUPPLIER_NONE.SPL_HIT

Counts any other requests that tbd

OTHER_ASSISTS.ANY

Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.

RESOURCE_STALLS.ANY

This event counts resource-related stall cycles. Reasons for stalls can be as follows: - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots) - *any* u-arch structure got empty (like INT/SIMD FreeLists) - FPU control word (FPCW), MXCSR and others. This counts cycles that the pipeline backend blocked uop delivery from the front end.

RESOURCE_STALLS.SB

This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.

RS_EVENTS.EMPTY_CYCLES

This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.

RS_EVENTS.EMPTY_END

Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.

RTM_RETIRED.ABORTED

Number of times RTM abort was triggered

RTM_RETIRED.ABORTED_EVENTS

Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)

RTM_RETIRED.ABORTED_MEM

Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)

RTM_RETIRED.ABORTED_MEMTYPE

Number of times an RTM execution aborted due to incompatible memory type

RTM_RETIRED.ABORTED_PS

Number of times RTM abort was triggered (PEBS)

RTM_RETIRED.ABORTED_TIMER

Number of times an RTM execution aborted due to uncommon conditions.

RTM_RETIRED.ABORTED_UNFRIENDLY

Number of times an RTM execution aborted due to HLE-unfriendly instructions

RTM_RETIRED.COMMIT

Number of times RTM commit succeeded

RTM_RETIRED.START

Number of times we entered an RTM region does not count nested transactions

TLB_FLUSH.DTLB_THREAD

This event counts the number of DTLB flush attempts of the thread-specific entries.

TLB_FLUSH.STLB_ANY

This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).

TX_EXEC.MISC1

Unfriendly TSX abort triggered by a flowmarker

TX_EXEC.MISC2

Unfriendly TSX abort triggered by a vzeroupper instruction

TX_EXEC.MISC3

Unfriendly TSX abort triggered by a nest count that is too deep

TX_EXEC.MISC4

RTM region detected inside HLE

TX_EXEC.MISC5

# HLE inside HLE+

TX_MEM.ABORT_CAPACITY

Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.

TX_MEM.ABORT_CONFLICT

Number of times a TSX line had a cache conflict

TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH

Number of times a TSX Abort was triggered due to release/commit but data and address mismatch

TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY

Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty

TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT

Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer

TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK

Number of times a TSX Abort was triggered due to a non-release/commit store to lock

TX_MEM.HLE_ELISION_BUFFER_FULL

Number of times we could not allocate Lock Buffer

UNC_ARB_COH_TRK_REQUESTS.ALL

Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.

UNC_ARB_TRK_OCCUPANCY.ALL

Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.

UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST

Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;

UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT

Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.

UNC_ARB_TRK_REQUESTS.ALL

Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.

UNC_ARB_TRK_REQUESTS.DRD_DIRECT

Number of Core coherent Data Read entries allocated in DirectData mode

UNC_ARB_TRK_REQUESTS.WRITES

Number of Writes allocated - any write transactions: full/partials writes and evictions.

UNC_CBO_CACHE_LOOKUP.ANY_ES

L3 Lookup any request that access cache and found line in E or S-state

UNC_CBO_CACHE_LOOKUP.ANY_I

L3 Lookup any request that access cache and found line in I-state

UNC_CBO_CACHE_LOOKUP.ANY_M

L3 Lookup any request that access cache and found line in M-state

UNC_CBO_CACHE_LOOKUP.ANY_MESI

L3 Lookup any request that access cache and found line in MESI-state

UNC_CBO_CACHE_LOOKUP.READ_ES

L3 Lookup read request that access cache and found line in E or S-state

UNC_CBO_CACHE_LOOKUP.READ_I

L3 Lookup read request that access cache and found line in I-state

UNC_CBO_CACHE_LOOKUP.READ_MESI

L3 Lookup read request that access cache and found line in any MESI-state

UNC_CBO_CACHE_LOOKUP.WRITE_ES

L3 Lookup write request that access cache and found line in E or S-state

UNC_CBO_CACHE_LOOKUP.WRITE_M

L3 Lookup write request that access cache and found line in M-state

UNC_CBO_CACHE_LOOKUP.WRITE_MESI

L3 Lookup write request that access cache and found line in MESI-state

UNC_CBO_XSNP_RESPONSE.HITM_XCORE

A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.

UNC_CBO_XSNP_RESPONSE.HIT_XCORE

A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.

UNC_CBO_XSNP_RESPONSE.MISS_EVICTION

A cross-core snoop resulted from L3 Eviction which misses in some processor core.

UNC_CBO_XSNP_RESPONSE.MISS_XCORE

A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.

UOPS_DISPATCHED_PORT.PORT_0

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.

UOPS_DISPATCHED_PORT.PORT_1

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.

UOPS_DISPATCHED_PORT.PORT_2

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.

UOPS_DISPATCHED_PORT.PORT_3

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.

UOPS_DISPATCHED_PORT.PORT_4

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.

UOPS_DISPATCHED_PORT.PORT_5

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.

UOPS_DISPATCHED_PORT.PORT_6

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.

UOPS_DISPATCHED_PORT.PORT_7

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.

UOPS_EXECUTED.CORE

Number of uops executed from any thread

UOPS_EXECUTED.CORE_CYCLES_GE_1

Cycles at least 1 micro-op is executed from any thread on physical core

UOPS_EXECUTED.CORE_CYCLES_GE_2

Cycles at least 2 micro-op is executed from any thread on physical core

UOPS_EXECUTED.CORE_CYCLES_GE_3

Cycles at least 3 micro-op is executed from any thread on physical core

UOPS_EXECUTED.CORE_CYCLES_GE_4

Cycles at least 4 micro-op is executed from any thread on physical core

UOPS_EXECUTED.CORE_CYCLES_NONE

Cycles with no micro-ops executed from any thread on physical core

UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC

Cycles where at least 1 uop was executed per-thread

UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC

Cycles where at least 2 uops were executed per-thread

UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC

Cycles where at least 3 uops were executed per-thread

UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC

Cycles where at least 4 uops were executed per-thread

UOPS_EXECUTED.STALL_CYCLES

This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.

UOPS_EXECUTED.THREAD

Number of uops to be executed per-thread each cycle.

UOPS_EXECUTED.X87

Counts the number of x87 uops dispatched.

UOPS_ISSUED.ANY

This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).

UOPS_ISSUED.SLOW_LEA

Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.

UOPS_ISSUED.STALL_CYCLES

This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.

UOPS_ISSUED.VECTOR_WIDTH_MISMATCH

This event counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to ?Mixing Intel AVX and Intel SSE Code? section of the Optimization Guide.

UOPS_RETIRED.RETIRE_SLOTS

This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.

UOPS_RETIRED.STALL_CYCLES

This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.

UOPS_RETIRED.TOTAL_CYCLES

Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.