Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help

Events for Intel® Microarchitecture Code Name Broadwell EP

This section provides reference for hardware events that can be monitored for the CPU(s):

The following performance-monitoring events are supported:

ARITH.FPU_DIV_ACTIVE

This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed

BACLEARS.ANY

Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.

BR_INST_EXEC.ALL_BRANCHES

This event counts both taken and not taken speculative and retired branch instructions.

BR_INST_EXEC.ALL_CONDITIONAL

This event counts both taken and not taken speculative and retired macro-conditional branch instructions.

BR_INST_EXEC.ALL_DIRECT_JMP

This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.

BR_INST_EXEC.ALL_DIRECT_NEAR_CALL

This event counts both taken and not taken speculative and retired direct near calls.

BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET

This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.

BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN

This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.

BR_INST_EXEC.NONTAKEN_CONDITIONAL

This event counts not taken macro-conditional branch instructions.

BR_INST_EXEC.TAKEN_CONDITIONAL

This event counts taken speculative and retired macro-conditional branch instructions.

BR_INST_EXEC.TAKEN_DIRECT_JUMP

This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.

BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL

This event counts taken speculative and retired direct near calls.

BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET

This event counts taken speculative and retired indirect branches excluding calls and return branches.

BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL

This event counts taken speculative and retired indirect calls including both register and memory indirect.

BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN

This event counts taken speculative and retired indirect branches that have a return mnemonic.

BR_INST_RETIRED.ALL_BRANCHES

This event counts all (macro) branch instructions retired.

BR_INST_RETIRED.ALL_BRANCHES_PS

This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.

BR_INST_RETIRED.CONDITIONAL

This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired.

BR_INST_RETIRED.CONDITIONAL_PS

This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.

BR_INST_RETIRED.FAR_BRANCH

This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired.

BR_INST_RETIRED.NEAR_CALL

This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired.

BR_INST_RETIRED.NEAR_CALL_PS

This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.

BR_INST_RETIRED.NEAR_CALL_R3

This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).

BR_INST_RETIRED.NEAR_CALL_R3_PS

This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).

BR_INST_RETIRED.NEAR_RETURN

This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired.

BR_INST_RETIRED.NEAR_RETURN_PS

This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.

BR_INST_RETIRED.NEAR_TAKEN

This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired.

BR_INST_RETIRED.NEAR_TAKEN_PS

This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.

BR_INST_RETIRED.NOT_TAKEN

This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.

BR_MISP_EXEC.ALL_BRANCHES

This event counts both taken and not taken speculative and retired mispredicted branch instructions.

BR_MISP_EXEC.ALL_CONDITIONAL

This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.

BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET

This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.

BR_MISP_EXEC.NONTAKEN_CONDITIONAL

This event counts not taken speculative and retired mispredicted macro conditional branch instructions.

BR_MISP_EXEC.TAKEN_CONDITIONAL

This event counts taken speculative and retired mispredicted macro conditional branch instructions.

BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET

This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.

BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL

Taken speculative and retired mispredicted indirect calls

BR_MISP_EXEC.TAKEN_RETURN_NEAR

This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.

BR_MISP_RETIRED.ALL_BRANCHES

This event counts all mispredicted macro branch instructions retired.

BR_MISP_RETIRED.ALL_BRANCHES_PS

This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.

BR_MISP_RETIRED.CONDITIONAL

This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired.

BR_MISP_RETIRED.CONDITIONAL_PS

This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.

BR_MISP_RETIRED.NEAR_TAKEN

number of near branch instructions retired that were mispredicted and taken.

BR_MISP_RETIRED.NEAR_TAKEN_PS

number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS)

BR_MISP_RETIRED.RET

This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.

BR_MISP_RETIRED.RET_PS

This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.

CPL_CYCLES.RING0

This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.

CPL_CYCLES.RING0_TRANS

This event counts when there is a transition from ring 1,2 or 3 to ring0.

CPL_CYCLES.RING123

This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.

CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE

Count XClk pulses when this thread is unhalted and the other thread is halted.

CPU_CLK_THREAD_UNHALTED.REF_XCLK

This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.

CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY

Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)

CPU_CLK_UNHALTED.REF_TSC

This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling ™' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case....

CPU_CLK_UNHALTED.THREAD

This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events...

CPU_CLK_UNHALTED.THREAD_ANY

Core cycles when at least one thread on the physical core is not in halt state

CPU_CLK_UNHALTED.THREAD_P

This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.

CPU_CLK_UNHALTED.THREAD_P_ANY

Core cycles when at least one thread on the physical core is not in halt state

CYCLE_ACTIVITY.CYCLES_L1D_MISS

Cycles while L1 cache miss demand load is outstanding.

CYCLE_ACTIVITY.CYCLES_L1D_PENDING

Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.

CYCLE_ACTIVITY.CYCLES_L2_MISS

Cycles while L2 cache miss demand load is outstanding.

CYCLE_ACTIVITY.CYCLES_L2_PENDING

Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.

CYCLE_ACTIVITY.CYCLES_LDM_PENDING

Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem)

CYCLE_ACTIVITY.CYCLES_MEM_ANY

Cycles while memory subsystem has an outstanding load.

CYCLE_ACTIVITY.CYCLES_NO_EXECUTE

Counts number of cycles nothing is executed on any execution port.

CYCLE_ACTIVITY.STALLS_L1D_MISS

Execution stalls while L1 cache miss demand load is outstanding.

CYCLE_ACTIVITY.STALLS_L1D_PENDING

Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.

CYCLE_ACTIVITY.STALLS_L2_MISS

Execution stalls while L2 cache miss demand load is outstanding.

CYCLE_ACTIVITY.STALLS_L2_PENDING

Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache. (as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands

CYCLE_ACTIVITY.STALLS_LDM_PENDING

Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.

CYCLE_ACTIVITY.STALLS_MEM_ANY

Execution stalls while memory subsystem has an outstanding load.

CYCLE_ACTIVITY.STALLS_TOTAL

Total execution stalls.

DSB2MITE_SWITCHES.PENALTY_CYCLES

This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0?2 cycles.

DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK

This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

DTLB_LOAD_MISSES.STLB_HIT

Load operations that miss the first DTLB level but hit the second and do not cause page walks

DTLB_LOAD_MISSES.STLB_HIT_2M

Load misses that miss the DTLB and hit the STLB (2M)

DTLB_LOAD_MISSES.STLB_HIT_4K

Load misses that miss the DTLB and hit the STLB (4K)

DTLB_LOAD_MISSES.WALK_COMPLETED

Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.

DTLB_LOAD_MISSES.WALK_COMPLETED_1G

This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.

DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M

This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.

DTLB_LOAD_MISSES.WALK_COMPLETED_4K

This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.

DTLB_LOAD_MISSES.WALK_DURATION

This event counts the number of cycles while PMH is busy with the page walk.

DTLB_STORE_MISSES.MISS_CAUSES_A_WALK

This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

DTLB_STORE_MISSES.STLB_HIT

Store operations that miss the first TLB level but hit the second and do not cause page walks

DTLB_STORE_MISSES.STLB_HIT_2M

Store misses that miss the DTLB and hit the STLB (2M)

DTLB_STORE_MISSES.STLB_HIT_4K

Store misses that miss the DTLB and hit the STLB (4K)

DTLB_STORE_MISSES.WALK_COMPLETED

Store misses in all DTLB levels that cause completed page walks

DTLB_STORE_MISSES.WALK_COMPLETED_1G

This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.

DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M

This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.

DTLB_STORE_MISSES.WALK_COMPLETED_4K

This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.

DTLB_STORE_MISSES.WALK_DURATION

This event counts the number of cycles while PMH is busy with the page walk.

EPT.WALK_CYCLES

This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.

FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE

Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE

Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE

Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE

Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.DOUBLE

Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?

FP_ARITH_INST_RETIRED.PACKED

Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.SCALAR

Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.SCALAR_DOUBLE

Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.SCALAR_SINGLE

Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.

FP_ARITH_INST_RETIRED.SINGLE

Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?

FP_ASSIST.ANY

This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.

FP_ASSIST.SIMD_INPUT

This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.

FP_ASSIST.SIMD_OUTPUT

This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.

FP_ASSIST.X87_INPUT

This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.

FP_ASSIST.X87_OUTPUT

This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.

HLE_RETIRED.ABORTED

Number of times HLE abort was triggered

HLE_RETIRED.ABORTED_MISC1

Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details)

HLE_RETIRED.ABORTED_MISC2

Number of times the TSX watchdog signaled an HLE abort

HLE_RETIRED.ABORTED_MISC3

Number of times a disallowed operation caused an HLE abort

HLE_RETIRED.ABORTED_MISC4

Number of times HLE caused a fault

HLE_RETIRED.ABORTED_MISC5

Number of times HLE aborted and was not due to the abort conditions in subevents 3-6

HLE_RETIRED.ABORTED_PS

Number of times HLE abort was triggered (PEBS)

HLE_RETIRED.COMMIT

Number of times HLE commit succeeded

HLE_RETIRED.START

Number of times we entered an HLE region; does not count nested transactions

ICACHE.HIT

This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.

ICACHE.IFDATA_STALL

This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).

ICACHE.MISSES

This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.

IDQ.ALL_DSB_CYCLES_4_UOPS

This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ.

IDQ.ALL_DSB_CYCLES_ANY_UOPS

This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ.

IDQ.ALL_MITE_CYCLES_4_UOPS

This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).

IDQ.ALL_MITE_CYCLES_ANY_UOPS

This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).

IDQ.DSB_CYCLES

This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ.

IDQ.DSB_UOPS

This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ.

IDQ.EMPTY

This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.

IDQ.MITE_ALL_UOPS

This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).

IDQ.MITE_CYCLES

This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ.

IDQ.MITE_UOPS

This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).

IDQ.MS_CYCLES

This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.

IDQ.MS_DSB_CYCLES

This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ.

IDQ.MS_DSB_OCCUR

This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ.

IDQ.MS_DSB_UOPS

This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ.

IDQ.MS_MITE_UOPS

This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ.

IDQ.MS_SWITCHES

Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer

IDQ.MS_UOPS

This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.

IDQ_UOPS_NOT_DELIVERED.CORE

This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread; b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); c. Instruction Decode Queue (IDQ) delivers four uops.

IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE

This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.

IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK

Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE

This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE

Cycles with less than 2 uops delivered by the front end

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE

Cycles with less than 3 uops delivered by the front end

ILD_STALL.LCP

This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.

INST_RETIRED.ANY

This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions...

INST_RETIRED.ANY_P

This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).

INST_RETIRED.PREC_DIST

This is a precise version (that is, uses PEBS) of the event that counts instructions retired.

INST_RETIRED.X87

This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.

INT_MISC.RAT_STALL_CYCLES

This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.

INT_MISC.RECOVERY_CYCLES

Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear

INT_MISC.RECOVERY_CYCLES_ANY

Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)

ITLB.ITLB_FLUSH

This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).

ITLB_MISSES.MISS_CAUSES_A_WALK

This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).

ITLB_MISSES.STLB_HIT

Operations that miss the first ITLB level but hit the second and do not cause any page walks

ITLB_MISSES.STLB_HIT_2M

Code misses that miss the DTLB and hit the STLB (2M)

ITLB_MISSES.STLB_HIT_4K

Core misses that miss the DTLB and hit the STLB (4K)

ITLB_MISSES.WALK_COMPLETED

Misses in all ITLB levels that cause completed page walks

ITLB_MISSES.WALK_COMPLETED_1G

This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.

ITLB_MISSES.WALK_COMPLETED_2M_4M

This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.

ITLB_MISSES.WALK_COMPLETED_4K

This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.

ITLB_MISSES.WALK_DURATION

This event counts the number of cycles while PMH is busy with the page walk.

L1D.REPLACEMENT

This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.

L1D_PEND_MISS.FB_FULL

Cycles a demand request was blocked due to Fill Buffers inavailability

L1D_PEND_MISS.PENDING

This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.

L1D_PEND_MISS.PENDING_CYCLES

This event counts duration of L1D miss outstanding in cycles.

L1D_PEND_MISS.PENDING_CYCLES_ANY

Cycles with L1D load Misses outstanding from any thread on physical core

L2_DEMAND_RQSTS.WB_HIT

This event counts the number of WB requests that hit L2 cache.

L2_LINES_IN.ALL

This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.

L2_LINES_IN.E

This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.

L2_LINES_IN.I

This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.

L2_LINES_IN.S

This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.

L2_LINES_OUT.DEMAND_CLEAN

Clean L2 cache lines evicted by demand

L2_RQSTS.ALL_CODE_RD

This event counts the total number of L2 code requests.

L2_RQSTS.ALL_DEMAND_DATA_RD

This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.

L2_RQSTS.ALL_DEMAND_MISS

Demand requests that miss L2 cache

L2_RQSTS.ALL_DEMAND_REFERENCES

Demand requests to L2 cache

L2_RQSTS.ALL_PF

This event counts the total number of requests from the L2 hardware prefetchers.

L2_RQSTS.ALL_RFO

This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.

L2_RQSTS.CODE_RD_HIT

L2 cache hits when fetching instructions, code reads.

L2_RQSTS.CODE_RD_MISS

L2 cache misses when fetching instructions

L2_RQSTS.DEMAND_DATA_RD_HIT

This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.

L2_RQSTS.DEMAND_DATA_RD_MISS

This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.

L2_RQSTS.L2_PF_HIT

This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types

L2_RQSTS.L2_PF_MISS

This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.

L2_RQSTS.MISS

All requests that miss L2 cache

L2_RQSTS.REFERENCES

All L2 requests

L2_RQSTS.RFO_HIT

RFO requests that hit L2 cache

L2_RQSTS.RFO_MISS

RFO requests that miss L2 cache

L2_TRANS.ALL_PF

This event counts L2 or L3 HW prefetches that access L2 cache including rejects.

L2_TRANS.ALL_REQUESTS

This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.

L2_TRANS.CODE_RD

This event counts the number of L2 cache accesses when fetching instructions.

L2_TRANS.DEMAND_DATA_RD

This event counts Demand Data Read requests that access L2 cache, including rejects.

L2_TRANS.L1D_WB

This event counts L1D writebacks that access L2 cache.

L2_TRANS.L2_FILL

This event counts L2 fill requests that access L2 cache.

L2_TRANS.L2_WB

This event counts L2 writebacks that access L2 cache.

L2_TRANS.RFO

This event counts Read for Ownership (RFO) requests that access L2 cache.

LD_BLOCKS.NO_SR

This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.

LD_BLOCKS.STORE_FORWARD

This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: - preceding store conflicts with the load (incomplete overlap); - store forwarding is impossible due to u-arch limitations; - preceding lock RMW operations are not forwarded; - store has the no-forward bit set (uncacheable/page-split/masked stores); - all-blocking stores are used (mostly, fences and port I/O); and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide.

LD_BLOCKS_PARTIAL.ADDRESS_ALIAS

This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.

LOAD_HIT_PRE.HW_PF

This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.

LOAD_HIT_PRE.SW_PF

This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.

LOCK_CYCLES.CACHE_LOCK_DURATION

This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).

LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION

This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.

LONGEST_LAT_CACHE.MISS

This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.

LONGEST_LAT_CACHE.REFERENCE

This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.

LSD.CYCLES_4_UOPS

Cycles 4 Uops delivered by the LSD, but didn't come from the decoder

LSD.CYCLES_ACTIVE

Cycles Uops delivered by the LSD, but didn't come from the decoder

LSD.UOPS

Number of Uops delivered by the LSD. Read more on LSD under LSD_REPLAY.REPLAY

MACHINE_CLEARS.COUNT

Number of machine clears (nukes) of any type.

MACHINE_CLEARS.CYCLES

This event counts both thread-specific (TS) and all-thread (AT) nukes.

MACHINE_CLEARS.MASKMOV

Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.

MACHINE_CLEARS.MEMORY_ORDERING

This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer.

MACHINE_CLEARS.SMC

This event counts self-modifying code (SMC) detected, which causes a machine clear.

MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.

MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).

MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).

MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.

MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.

MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.

MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.

MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.

MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM

Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)

MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS

tbd

MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM

Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)

MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS

tbd

MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD

Retired load uop whose Data Source was: forwarded from remote cache

MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS

tbd

MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM

Retired load uop whose Data Source was: Remote cache HITM

MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS

tbd

MEM_LOAD_UOPS_RETIRED.HIT_LFB

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.

MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.

MEM_LOAD_UOPS_RETIRED.L1_HIT

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source

MEM_LOAD_UOPS_RETIRED.L1_HIT_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source

MEM_LOAD_UOPS_RETIRED.L1_MISS

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.

MEM_LOAD_UOPS_RETIRED.L1_MISS_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.

MEM_LOAD_UOPS_RETIRED.L2_HIT

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.

MEM_LOAD_UOPS_RETIRED.L2_HIT_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.

MEM_LOAD_UOPS_RETIRED.L2_MISS

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.

MEM_LOAD_UOPS_RETIRED.L2_MISS_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.

MEM_LOAD_UOPS_RETIRED.L3_HIT

This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.

MEM_LOAD_UOPS_RETIRED.L3_HIT_PS

This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.

MEM_LOAD_UOPS_RETIRED.L3_MISS

Miss in last-level (L3) cache. Excludes Unknown data-source.

MEM_LOAD_UOPS_RETIRED.L3_MISS_PS

Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128

This event counts loads with latency value being above 128.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16

This event counts loads with latency value being above 16.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256

This event counts loads with latency value being above 256.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32

This event counts loads with latency value being above 32.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4

This event counts loads with latency value being above four.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512

This event counts loads with latency value being above 512.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64

This event counts loads with latency value being above 64.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8

This event counts loads with latency value being above eight.

MEM_UOPS_RETIRED.ALL_LOADS

This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.

MEM_UOPS_RETIRED.ALL_LOADS_PS

This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.

MEM_UOPS_RETIRED.ALL_STORES

This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.

MEM_UOPS_RETIRED.ALL_STORES_PS

This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.

MEM_UOPS_RETIRED.LOCK_LOADS

This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with locked access retired to the architected path.

MEM_UOPS_RETIRED.LOCK_LOADS_PS

This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.

MEM_UOPS_RETIRED.SPLIT_LOADS

This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).

MEM_UOPS_RETIRED.SPLIT_LOADS_PS

This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).

MEM_UOPS_RETIRED.SPLIT_STORES

This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).

MEM_UOPS_RETIRED.SPLIT_STORES_PS

This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).

MEM_UOPS_RETIRED.STLB_MISS_LOADS

This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.

MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS

This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.

MEM_UOPS_RETIRED.STLB_MISS_STORES

This is a non-precise version (that is, does not use PEBS) of the event that counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.

MEM_UOPS_RETIRED.STLB_MISS_STORES_PS

This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.

MISALIGN_MEM_REF.LOADS

This event counts speculative cache-line split load uops dispatched to the L1 cache.

MISALIGN_MEM_REF.STORES

This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.

MOVE_ELIMINATION.INT_ELIMINATED

Number of integer Move Elimination candidate uops that were eliminated.

MOVE_ELIMINATION.INT_NOT_ELIMINATED

Number of integer Move Elimination candidate uops that were not eliminated.

MOVE_ELIMINATION.SIMD_ELIMINATED

Number of SIMD Move Elimination candidate uops that were eliminated.

MOVE_ELIMINATION.SIMD_NOT_ELIMINATED

Number of SIMD Move Elimination candidate uops that were not eliminated.

OFFCORE_REQUESTS.ALL_DATA_RD

This event counts the demand and prefetch data reads. All Core Data Reads include cacheable "Demands" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.

OFFCORE_REQUESTS.DEMAND_CODE_RD

This event counts both cacheable and noncachaeble code read requests.

OFFCORE_REQUESTS.DEMAND_DATA_RD

This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.

OFFCORE_REQUESTS.DEMAND_RFO

This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.

OFFCORE_REQUESTS_BUFFER.SQ_FULL

This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full. Note: Writeback pending FIFO has six entries.

OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD

This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD

This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD

This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO

This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The "Offcore outstanding" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD

This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The "Offcore outstanding" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD

This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS. Note: A prefetch promoted to Demand is counted from the promotion point.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6

Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO

This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.

OFFCORE_RESPONSE

tbd

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.ANY_RESPONSE

Counts all demand & prefetch code reads that hit in the L3

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts all demand & prefetch code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all demand & prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.SNOOP_MISS

Counts all demand & prefetch code reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.ANY_DRAM

Counts all demand & prefetch code reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.ANY_RESPONSE

Counts all demand & prefetch code reads that miss in the L3

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.LOCAL_DRAM

Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.REMOTE_DRAM

Counts all demand & prefetch code reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.REMOTE_HITM

Counts all demand & prefetch code reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all demand & prefetch code reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.ANY_RESPONSE

Counts all demand & prefetch data reads that hit in the L3

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.SNOOP_MISS

Counts all demand & prefetch data reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.ANY_DRAM

Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.ANY_RESPONSE

Counts all demand & prefetch data reads that miss in the L3

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.LOCAL_DRAM

Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.REMOTE_DRAM

Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.REMOTE_HITM

Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.ANY_RESPONSE

Counts all prefetch code reads that hit in the L3

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts all prefetch code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.SNOOP_MISS

Counts all prefetch code reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.ANY_DRAM

Counts all prefetch code reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.ANY_RESPONSE

Counts all prefetch code reads that miss in the L3

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.LOCAL_DRAM

Counts all prefetch code reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.REMOTE_DRAM

Counts all prefetch code reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.REMOTE_HITM

Counts all prefetch code reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all prefetch code reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.ANY_RESPONSE

Counts all prefetch data reads that hit in the L3

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.SNOOP_MISS

Counts all prefetch data reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.ANY_DRAM

Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.ANY_RESPONSE

Counts all prefetch data reads that miss in the L3

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.LOCAL_DRAM

Counts all prefetch data reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.REMOTE_DRAM

Counts all prefetch data reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.REMOTE_HITM

Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.ANY_RESPONSE

Counts prefetch RFOs that hit in the L3

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.HITM_OTHER_CORE

Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.NO_SNOOP_NEEDED

Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.SNOOP_MISS

Counts prefetch RFOs that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.ANY_DRAM

Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.ANY_RESPONSE

Counts prefetch RFOs that miss in the L3

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.LOCAL_DRAM

Counts prefetch RFOs that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.REMOTE_DRAM

Counts prefetch RFOs that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.REMOTE_HITM

Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.ANY_RESPONSE

Counts all data/code/rfo reads (demand & prefetch) that hit in the L3

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.HITM_OTHER_CORE

Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.SNOOP_MISS

Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.ANY_DRAM

Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.ANY_RESPONSE

Counts all data/code/rfo reads (demand & prefetch) that miss in the L3

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.LOCAL_DRAM

Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.REMOTE_DRAM

Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.REMOTE_HITM

Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.ANY_RESPONSE

Counts all requests that hit in the L3

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.HITM_OTHER_CORE

Counts all requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.SNOOP_MISS

Counts all requests that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.ANY_DRAM

Counts all requests that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.ANY_RESPONSE

Counts all requests that miss in the L3

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.LOCAL_DRAM

Counts all requests that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.REMOTE_DRAM

Counts all requests that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.REMOTE_HITM

Counts all requests that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all requests that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.ANY_RESPONSE

Counts all demand & prefetch RFOs that hit in the L3

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.HITM_OTHER_CORE

Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.SNOOP_MISS

Counts all demand & prefetch RFOs that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.ANY_DRAM

Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.ANY_RESPONSE

Counts all demand & prefetch RFOs that miss in the L3

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.LOCAL_DRAM

Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.REMOTE_DRAM

Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.REMOTE_HITM

Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.ANY_RESPONSE

Counts writebacks (modified to exclusive) that hit in the L3

OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.HITM_OTHER_CORE

Counts writebacks (modified to exclusive) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.NO_SNOOP_NEEDED

Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.SNOOP_MISS

Counts writebacks (modified to exclusive) that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.ANY_DRAM

Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.ANY_RESPONSE

Counts writebacks (modified to exclusive) that miss in the L3

OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.LOCAL_DRAM

Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.REMOTE_DRAM

Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.REMOTE_HITM

Counts writebacks (modified to exclusive) that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts writebacks (modified to exclusive) that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.ANY_RESPONSE

Counts all demand code reads that hit in the L3

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.SNOOP_MISS

Counts all demand code reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.ANY_DRAM

Counts all demand code reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.ANY_RESPONSE

Counts all demand code reads that miss in the L3

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.LOCAL_DRAM

Counts all demand code reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.REMOTE_DRAM

Counts all demand code reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.REMOTE_HITM

Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.ANY_RESPONSE

Counts demand data reads that hit in the L3

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.SNOOP_MISS

Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.ANY_DRAM

Counts demand data reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.ANY_RESPONSE

Counts demand data reads that miss in the L3

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.LOCAL_DRAM

Counts demand data reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.REMOTE_DRAM

Counts demand data reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.REMOTE_HITM

Counts demand data reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.ANY_RESPONSE

Counts all demand data writes (RFOs) that hit in the L3

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.HITM_OTHER_CORE

Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.SNOOP_MISS

Counts all demand data writes (RFOs) that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.ANY_DRAM

Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.ANY_RESPONSE

Counts all demand data writes (RFOs) that miss in the L3

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.LOCAL_DRAM

Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.REMOTE_DRAM

Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.REMOTE_HITM

Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.ANY_RESPONSE

Counts any other requests that hit in the L3

OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.HITM_OTHER_CORE

Counts any other requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.NO_SNOOP_NEEDED

Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.SNOOP_MISS

Counts any other requests that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.ANY_DRAM

Counts any other requests that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.ANY_RESPONSE

Counts any other requests that miss in the L3

OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.LOCAL_DRAM

Counts any other requests that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.REMOTE_DRAM

Counts any other requests that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.REMOTE_HITM

Counts any other requests that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts any other requests that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.ANY_RESPONSE

Counts all prefetch (that bring data to LLC only) code reads that hit in the L3

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.SNOOP_MISS

Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.ANY_DRAM

Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.ANY_RESPONSE

Counts all prefetch (that bring data to LLC only) code reads that miss in the L3

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.LOCAL_DRAM

Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.REMOTE_DRAM

Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.REMOTE_HITM

Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.ANY_RESPONSE

Counts prefetch (that bring data to L2) data reads that hit in the L3

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.SNOOP_MISS

Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.ANY_DRAM

Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.ANY_RESPONSE

Counts prefetch (that bring data to L2) data reads that miss in the L3

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.LOCAL_DRAM

Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.REMOTE_DRAM

Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.REMOTE_HITM

Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.ANY_RESPONSE

Counts all prefetch (that bring data to L2) RFOs that hit in the L3

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.HITM_OTHER_CORE

Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.SNOOP_MISS

Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.ANY_DRAM

Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.ANY_RESPONSE

Counts all prefetch (that bring data to L2) RFOs that miss in the L3

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.LOCAL_DRAM

Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.REMOTE_DRAM

Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.REMOTE_HITM

Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.ANY_RESPONSE

Counts prefetch (that bring data to LLC only) code reads that hit in the L3

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.SNOOP_MISS

Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.ANY_DRAM

Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.ANY_RESPONSE

Counts prefetch (that bring data to LLC only) code reads that miss in the L3

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.LOCAL_DRAM

Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.REMOTE_DRAM

Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.REMOTE_HITM

Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts prefetch (that bring data to LLC only) code reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.ANY_RESPONSE

Counts all prefetch (that bring data to LLC only) data reads that hit in the L3

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE

Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.SNOOP_MISS

Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.ANY_DRAM

Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.ANY_RESPONSE

Counts all prefetch (that bring data to LLC only) data reads that miss in the L3

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.LOCAL_DRAM

Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.REMOTE_DRAM

Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.REMOTE_HITM

Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.ANY_RESPONSE

Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.HITM_OTHER_CORE

Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.SNOOP_MISS

Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.ANY_DRAM

Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.ANY_RESPONSE

Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.LOCAL_DRAM

Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.REMOTE_DRAM

Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.REMOTE_HITM

Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_HIT.ANY_RESPONSE

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that hit in the L3

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_HIT.HITM_OTHER_CORE

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_HIT.SNOOP_MISS

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_MISS.ANY_DRAM

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_MISS.ANY_RESPONSE

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that miss in the L3

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_MISS.LOCAL_DRAM

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_MISS.REMOTE_DRAM

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_MISS.REMOTE_HITM

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=SPLIT_LOCK_UC_LOCK:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all locks that are either split across cache line boundaries or to uncacheable addresses that miss the L3 and clean or shared data is transferred from remote cache

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_HIT.ANY_RESPONSE

Counts all non-temporal stores that hit in the L3

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_HIT.HITM_OTHER_CORE

Counts all non-temporal stores that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD

Counts all non-temporal stores that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_HIT.NO_SNOOP_NEEDED

Counts all non-temporal stores that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_HIT.SNOOP_MISS

Counts all non-temporal stores that hit in the L3 and the snoops sent to sibling cores return clean response

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_MISS.ANY_DRAM

Counts all non-temporal stores that miss the L3 and the data is returned from local or remote dram

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_MISS.ANY_RESPONSE

Counts all non-temporal stores that miss in the L3

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_MISS.LOCAL_DRAM

Counts all non-temporal stores that miss the L3 and the data is returned from local dram

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_MISS.REMOTE_DRAM

Counts all non-temporal stores that miss the L3 and the data is returned from remote dram

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_MISS.REMOTE_HITM

Counts all non-temporal stores that miss the L3 and the modified data is transferred from remote cache

OFFCORE_RESPONSE:request=STREAMING_STORES:response=LLC_MISS.REMOTE_HIT_FORWARD

Counts all non-temporal stores that miss the L3 and clean or shared data is transferred from remote cache

OTHER_ASSISTS.ANY_WB_ASSIST

Number of times any microcode assist is invoked by HW upon uop writeback.

OTHER_ASSISTS.AVX_TO_SSE

This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.

OTHER_ASSISTS.SSE_TO_AVX

This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.

PAGE_WALKER_LOADS.DTLB_L1

Number of DTLB page walker hits in the L1+FB

PAGE_WALKER_LOADS.DTLB_L2

Number of DTLB page walker hits in the L2

PAGE_WALKER_LOADS.DTLB_L3

Number of DTLB page walker hits in the L3 + XSNP

PAGE_WALKER_LOADS.DTLB_MEMORY

Number of DTLB page walker hits in Memory

PAGE_WALKER_LOADS.ITLB_L1

Number of ITLB page walker hits in the L1+FB

PAGE_WALKER_LOADS.ITLB_L2

Number of ITLB page walker hits in the L2

PAGE_WALKER_LOADS.ITLB_L3

Number of ITLB page walker hits in the L3 + XSNP

RESOURCE_STALLS.ANY

This event counts resource-related stall cycles. Reasons for stalls can be as follows: - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots) - *any* u-arch structure got empty (like INT/SIMD FreeLists) - FPU control word (FPCW), MXCSR and others. This counts cycles that the pipeline backend blocked uop delivery from the front end.

RESOURCE_STALLS.ROB

This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.

RESOURCE_STALLS.RS

This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.

RESOURCE_STALLS.SB

This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.

ROB_MISC_EVENTS.LBR_INSERTS

This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.

RS_EVENTS.EMPTY_CYCLES

This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.

RS_EVENTS.EMPTY_END

Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.

RTM_RETIRED.ABORTED

Number of times RTM abort was triggered

RTM_RETIRED.ABORTED_MISC1

Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details)

RTM_RETIRED.ABORTED_MISC2

Number of times the TSX watchdog signaled an RTM abort

RTM_RETIRED.ABORTED_MISC3

Number of times a disallowed operation caused an RTM abort

RTM_RETIRED.ABORTED_MISC4

Number of times a RTM caused a fault

RTM_RETIRED.ABORTED_MISC5

Number of times RTM aborted and was not due to the abort conditions in subevents 3-6

RTM_RETIRED.ABORTED_PS

Number of times RTM abort was triggered (PEBS)

RTM_RETIRED.COMMIT

Number of times RTM commit succeeded

RTM_RETIRED.START

Number of times we entered an RTM region; does not count nested transactions

TLB_FLUSH.DTLB_THREAD

This event counts the number of DTLB flush attempts of the thread-specific entries.

TLB_FLUSH.STLB_ANY

This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).

TX_EXEC.MISC1

Unfriendly TSX abort triggered by a flowmarker

TX_EXEC.MISC2

Unfriendly TSX abort triggered by a vzeroupper instruction

TX_EXEC.MISC3

Unfriendly TSX abort triggered by a nest count that is too deep

TX_EXEC.MISC4

RTM region detected inside HLE

TX_EXEC.MISC5

# HLE inside HLE+

TX_MEM.ABORT_CAPACITY_WRITE

Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow

TX_MEM.ABORT_CONFLICT

Number of times a TSX line had a cache conflict

TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH

Number of times a TSX Abort was triggered due to release/commit but data and address mismatch

TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY

Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty

TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT

Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer

TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK

Number of times a TSX Abort was triggered due to a non-release/commit store to lock

TX_MEM.HLE_ELISION_BUFFER_FULL

Number of times we could not allocate Lock Buffer

UNC_C_BOUNCE_CONTROL

Bounce Control

UNC_C_CLOCKTICKS

Uncore Clocks

UNC_C_COUNTER0_OCCUPANCY

Counter 0 Occupancy

UNC_C_FAST_ASSERTED

FaST wire asserted

UNC_C_LLC_LOOKUP.ANY

Cache Lookups; Any Request

UNC_C_LLC_LOOKUP.DATA_READ

Cache Lookups; Data Read Request

UNC_C_LLC_LOOKUP.NID

Cache Lookups; Lookups that Match NID

UNC_C_LLC_LOOKUP.READ

Cache Lookups; Any Read Request

UNC_C_LLC_LOOKUP.REMOTE_SNOOP

Cache Lookups; External Snoop Request

UNC_C_LLC_LOOKUP.WRITE

Cache Lookups; Write Requests

UNC_C_LLC_VICTIMS.E_STATE

Lines Victimized; Lines in E state

UNC_C_LLC_VICTIMS.F_STATE

Lines Victimized

UNC_C_LLC_VICTIMS.I_STATE

Lines Victimized; Lines in S State

UNC_C_LLC_VICTIMS.MISS

Lines Victimized

UNC_C_LLC_VICTIMS.M_STATE

Lines Victimized; Lines in M state

UNC_C_LLC_VICTIMS.NID

Lines Victimized; Victimized Lines that Match NID

UNC_C_MISC.CVZERO_PREFETCH_MISS

Cbo Misc; DRd hitting non-M with raw CV=0

UNC_C_MISC.CVZERO_PREFETCH_VICTIM

Cbo Misc; Clean Victim with raw CV=0

UNC_C_MISC.RFO_HIT_S

Cbo Misc; RFO HitS

UNC_C_MISC.RSPI_WAS_FSE

Cbo Misc; Silent Snoop Eviction

UNC_C_MISC.STARTED

Cbo Misc

UNC_C_MISC.WC_ALIASING

Cbo Misc; Write Combining Aliasing

UNC_C_QLRU.AGE0

LRU Queue; LRU Age 0

UNC_C_QLRU.AGE1

LRU Queue; LRU Age 1

UNC_C_QLRU.AGE2

LRU Queue; LRU Age 2

UNC_C_QLRU.AGE3

LRU Queue; LRU Age 3

UNC_C_QLRU.LRU_DECREMENT

LRU Queue; LRU Bits Decremented

UNC_C_QLRU.VICTIM_NON_ZERO

LRU Queue; Non-0 Aged Victim

UNC_C_RING_AD_USED.ALL

AD Ring In Use; All

UNC_C_RING_AD_USED.DOWN

AD Ring In Use; Down

UNC_C_RING_AD_USED.DOWN_EVEN

AD Ring In Use; Down and Even

UNC_C_RING_AD_USED.DOWN_ODD

AD Ring In Use; Down and Odd

UNC_C_RING_AD_USED.UP

AD Ring In Use; Up

UNC_C_RING_AD_USED.UP_EVEN

AD Ring In Use; Up and Even

UNC_C_RING_AD_USED.UP_ODD

AD Ring In Use; Up and Odd

UNC_C_RING_AK_USED.ALL

AK Ring In Use; All

UNC_C_RING_AK_USED.DOWN

AK Ring In Use; Down

UNC_C_RING_AK_USED.DOWN_EVEN

AK Ring In Use; Down and Even

UNC_C_RING_AK_USED.DOWN_ODD

AK Ring In Use; Down and Odd

UNC_C_RING_AK_USED.UP

AK Ring In Use; Up

UNC_C_RING_AK_USED.UP_EVEN

AK Ring In Use; Up and Even

UNC_C_RING_AK_USED.UP_ODD

AK Ring In Use; Up and Odd

UNC_C_RING_BL_USED.ALL

BL Ring in Use; Down

UNC_C_RING_BL_USED.DOWN

BL Ring in Use; Down

UNC_C_RING_BL_USED.DOWN_EVEN

BL Ring in Use; Down and Even

UNC_C_RING_BL_USED.DOWN_ODD

BL Ring in Use; Down and Odd

UNC_C_RING_BL_USED.UP

BL Ring in Use; Up

UNC_C_RING_BL_USED.UP_EVEN

BL Ring in Use; Up and Even

UNC_C_RING_BL_USED.UP_ODD

BL Ring in Use; Up and Odd

UNC_C_RING_BOUNCES.AD

Number of LLC responses that bounced on the Ring.; AD

UNC_C_RING_BOUNCES.AK

Number of LLC responses that bounced on the Ring.; AK

UNC_C_RING_BOUNCES.BL

Number of LLC responses that bounced on the Ring.; BL

UNC_C_RING_BOUNCES.IV

Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.

UNC_C_RING_IV_USED.ANY

BL Ring in Use; Any

UNC_C_RING_IV_USED.DN

BL Ring in Use; Any

UNC_C_RING_IV_USED.DOWN

BL Ring in Use; Down

UNC_C_RING_IV_USED.UP

BL Ring in Use; Any

UNC_C_RING_SINK_STARVED.AD

AD

UNC_C_RING_SINK_STARVED.AK

AK

UNC_C_RING_SINK_STARVED.BL

BL

UNC_C_RING_SINK_STARVED.IV

IV

UNC_C_RING_SRC_THRTL

Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.

UNC_C_RxR_EXT_STARVED.IPQ

Ingress Arbiter Blocking Cycles; IRQ

UNC_C_RxR_EXT_STARVED.IRQ

Ingress Arbiter Blocking Cycles; IPQ

UNC_C_RxR_EXT_STARVED.ISMQ_BIDS

Ingress Arbiter Blocking Cycles; ISMQ_BID

UNC_C_RxR_EXT_STARVED.PRQ

Ingress Arbiter Blocking Cycles; PRQ

UNC_C_RxR_INSERTS.IPQ

Ingress Allocations; IPQ

UNC_C_RxR_INSERTS.IRQ

Ingress Allocations; IRQ

UNC_C_RxR_INSERTS.IRQ_REJ

Ingress Allocations; IRQ Rejected

UNC_C_RxR_INSERTS.PRQ

Ingress Allocations; PRQ

UNC_C_RxR_INSERTS.PRQ_REJ

Ingress Allocations; PRQ

UNC_C_RxR_INT_STARVED.IPQ

Ingress Internal Starvation Cycles; IPQ

UNC_C_RxR_INT_STARVED.IRQ

Ingress Internal Starvation Cycles; IRQ

UNC_C_RxR_INT_STARVED.ISMQ

Ingress Internal Starvation Cycles; ISMQ

UNC_C_RxR_INT_STARVED.PRQ

Ingress Internal Starvation Cycles; PRQ

UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT

Probe Queue Retries; Address Conflict

UNC_C_RxR_IPQ_RETRY.ANY

Probe Queue Retries; Any Reject

UNC_C_RxR_IPQ_RETRY.FULL

Probe Queue Retries; No Egress Credits

UNC_C_RxR_IPQ_RETRY.QPI_CREDITS

Probe Queue Retries; No QPI Credits

UNC_C_RxR_IPQ_RETRY2.AD_SBO

Probe Queue Retries; No AD Sbo Credits

UNC_C_RxR_IPQ_RETRY2.TARGET

Probe Queue Retries; Target Node Filter

UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT

Ingress Request Queue Rejects; Address Conflict

UNC_C_RxR_IRQ_RETRY.ANY

Ingress Request Queue Rejects; Any Reject

UNC_C_RxR_IRQ_RETRY.FULL

Ingress Request Queue Rejects; No Egress Credits

UNC_C_RxR_IRQ_RETRY.IIO_CREDITS

Ingress Request Queue Rejects; No IIO Credits

UNC_C_RxR_IRQ_RETRY.NID

Ingress Request Queue Rejects

UNC_C_RxR_IRQ_RETRY.QPI_CREDITS

Ingress Request Queue Rejects; No QPI Credits

UNC_C_RxR_IRQ_RETRY.RTID

Ingress Request Queue Rejects; No RTIDs

UNC_C_RxR_IRQ_RETRY2.AD_SBO

Ingress Request Queue Rejects; No AD Sbo Credits

UNC_C_RxR_IRQ_RETRY2.BL_SBO

Ingress Request Queue Rejects; No BL Sbo Credits

UNC_C_RxR_IRQ_RETRY2.TARGET

Ingress Request Queue Rejects; Target Node Filter

UNC_C_RxR_ISMQ_RETRY.ANY

ISMQ Retries; Any Reject

UNC_C_RxR_ISMQ_RETRY.FULL

ISMQ Retries; No Egress Credits

UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS

ISMQ Retries; No IIO Credits

UNC_C_RxR_ISMQ_RETRY.NID

ISMQ Retries

UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS

ISMQ Retries; No QPI Credits

UNC_C_RxR_ISMQ_RETRY.RTID

ISMQ Retries; No RTIDs

UNC_C_RxR_ISMQ_RETRY.WB_CREDITS

ISMQ Retries

UNC_C_RxR_ISMQ_RETRY2.AD_SBO

ISMQ Request Queue Rejects; No AD Sbo Credits

UNC_C_RxR_ISMQ_RETRY2.BL_SBO

ISMQ Request Queue Rejects; No BL Sbo Credits

UNC_C_RxR_ISMQ_RETRY2.TARGET

ISMQ Request Queue Rejects; Target Node Filter

UNC_C_RxR_OCCUPANCY.IPQ

Ingress Occupancy; IPQ

UNC_C_RxR_OCCUPANCY.IRQ

Ingress Occupancy; IRQ

UNC_C_RxR_OCCUPANCY.IRQ_REJ

Ingress Occupancy; IRQ Rejected

UNC_C_RxR_OCCUPANCY.PRQ_REJ

Ingress Occupancy; PRQ Rejects

UNC_C_SBO_CREDITS_ACQUIRED.AD

SBo Credits Acquired; For AD Ring

UNC_C_SBO_CREDITS_ACQUIRED.BL

SBo Credits Acquired; For BL Ring

UNC_C_SBO_CREDIT_OCCUPANCY.AD

SBo Credits Occupancy; For AD Ring

UNC_C_SBO_CREDIT_OCCUPANCY.BL

SBo Credits Occupancy; For BL Ring

UNC_C_TOR_INSERTS.ALL

TOR Inserts; All

UNC_C_TOR_INSERTS.EVICTION

TOR Inserts; Evictions

UNC_C_TOR_INSERTS.LOCAL

TOR Inserts; Local Memory

UNC_C_TOR_INSERTS.LOCAL_OPCODE

TOR Inserts; Local Memory - Opcode Matched

UNC_C_TOR_INSERTS.MISS_LOCAL

TOR Inserts; Misses to Local Memory

UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE

TOR Inserts; Misses to Local Memory - Opcode Matched

UNC_C_TOR_INSERTS.MISS_OPCODE

TOR Inserts; Miss Opcode Match

UNC_C_TOR_INSERTS.MISS_REMOTE

TOR Inserts; Misses to Remote Memory

UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE

TOR Inserts; Misses to Remote Memory - Opcode Matched

UNC_C_TOR_INSERTS.NID_ALL

TOR Inserts; NID Matched

UNC_C_TOR_INSERTS.NID_EVICTION

TOR Inserts; NID Matched Evictions

UNC_C_TOR_INSERTS.NID_MISS_ALL

TOR Inserts; NID Matched Miss All

UNC_C_TOR_INSERTS.NID_MISS_OPCODE

TOR Inserts; NID and Opcode Matched Miss

UNC_C_TOR_INSERTS.NID_OPCODE

TOR Inserts; NID and Opcode Matched

UNC_C_TOR_INSERTS.NID_WB

TOR Inserts; NID Matched Writebacks

UNC_C_TOR_INSERTS.OPCODE

TOR Inserts; Opcode Match

UNC_C_TOR_INSERTS.REMOTE

TOR Inserts; Remote Memory

UNC_C_TOR_INSERTS.REMOTE_OPCODE

TOR Inserts; Remote Memory - Opcode Matched

UNC_C_TOR_INSERTS.WB

TOR Inserts; Writebacks

UNC_C_TOR_OCCUPANCY.ALL

TOR Occupancy; Any

UNC_C_TOR_OCCUPANCY.EVICTION

TOR Occupancy; Evictions

UNC_C_TOR_OCCUPANCY.LOCAL

TOR Occupancy

UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE

TOR Occupancy; Local Memory - Opcode Matched

UNC_C_TOR_OCCUPANCY.MISS_ALL

TOR Occupancy; Miss All

UNC_C_TOR_OCCUPANCY.MISS_LOCAL

TOR Occupancy

UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE

TOR Occupancy; Misses to Local Memory - Opcode Matched

UNC_C_TOR_OCCUPANCY.MISS_OPCODE

TOR Occupancy; Miss Opcode Match

UNC_C_TOR_OCCUPANCY.MISS_REMOTE

TOR Occupancy

UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE

TOR Occupancy; Misses to Remote Memory - Opcode Matched

UNC_C_TOR_OCCUPANCY.NID_ALL

TOR Occupancy; NID Matched

UNC_C_TOR_OCCUPANCY.NID_EVICTION

TOR Occupancy; NID Matched Evictions

UNC_C_TOR_OCCUPANCY.NID_MISS_ALL

TOR Occupancy; NID Matched

UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE

TOR Occupancy; NID and Opcode Matched Miss

UNC_C_TOR_OCCUPANCY.NID_OPCODE

TOR Occupancy; NID and Opcode Matched

UNC_C_TOR_OCCUPANCY.NID_WB

TOR Occupancy; NID Matched Writebacks

UNC_C_TOR_OCCUPANCY.OPCODE

TOR Occupancy; Opcode Match

UNC_C_TOR_OCCUPANCY.REMOTE

TOR Occupancy

UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE

TOR Occupancy; Remote Memory - Opcode Matched

UNC_C_TOR_OCCUPANCY.WB

TOR Occupancy; Writebacks

UNC_C_TxR_ADS_USED.AD

Onto AD Ring

UNC_C_TxR_ADS_USED.AK

Onto AK Ring

UNC_C_TxR_ADS_USED.BL

Onto BL Ring

UNC_C_TxR_INSERTS.AD_CACHE

Egress Allocations; AD - Cachebo

UNC_C_TxR_INSERTS.AD_CORE

Egress Allocations; AD - Corebo

UNC_C_TxR_INSERTS.AK_CACHE

Egress Allocations; AK - Cachebo

UNC_C_TxR_INSERTS.AK_CORE

Egress Allocations; AK - Corebo

UNC_C_TxR_INSERTS.BL_CACHE

Egress Allocations; BL - Cacheno

UNC_C_TxR_INSERTS.BL_CORE

Egress Allocations; BL - Corebo

UNC_C_TxR_INSERTS.IV_CACHE

Egress Allocations; IV - Cachebo

UNC_C_TxR_STARVED.AD_CORE

Injection Starvation; Onto AD Ring (to core)

UNC_C_TxR_STARVED.AK_BOTH

Injection Starvation; Onto AK Ring

UNC_C_TxR_STARVED.BL_BOTH

Injection Starvation; Onto BL Ring

UNC_C_TxR_STARVED.IV

Injection Starvation; Onto IV Ring

UNC_H_ADDR_OPC_MATCH.AD

QPI Address/Opcode Match; AD Opcodes

UNC_H_ADDR_OPC_MATCH.ADDR

QPI Address/Opcode Match; Address

UNC_H_ADDR_OPC_MATCH.AK

QPI Address/Opcode Match; AK Opcodes

UNC_H_ADDR_OPC_MATCH.BL

QPI Address/Opcode Match; BL Opcodes

UNC_H_ADDR_OPC_MATCH.FILT

QPI Address/Opcode Match; Address & Opcode Match

UNC_H_ADDR_OPC_MATCH.OPC

QPI Address/Opcode Match; Opcode

UNC_H_BT_CYCLES_NE

BT Cycles Not Empty

UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD

BT to HT Not Issued; Incoming Data Hazard

UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD

BT to HT Not Issued; Incoming Snoop Hazard

UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD

BT to HT Not Issued; Incoming Data Hazard

UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD

BT to HT Not Issued; Incoming Data Hazard

UNC_H_BYPASS_IMC.NOT_TAKEN

HA to iMC Bypass; Not Taken

UNC_H_BYPASS_IMC.TAKEN

HA to iMC Bypass; Taken

UNC_H_CLOCKTICKS

uclks

UNC_H_DIRECT2CORE_COUNT

Direct2Core Messages Sent

UNC_H_DIRECT2CORE_CYCLES_DISABLED

Cycles when Direct2Core was Disabled

UNC_H_DIRECT2CORE_TXN_OVERRIDE

Number of Reads that had Direct2Core Overridden

UNC_H_DIRECTORY_LAT_OPT

Directory Lat Opt Return

UNC_H_DIRECTORY_LOOKUP.NO_SNP

Directory Lookups; Snoop Not Needed

UNC_H_DIRECTORY_LOOKUP.SNP

Directory Lookups; Snoop Needed

UNC_H_DIRECTORY_UPDATE.ANY

Directory Updates; Any Directory Update

UNC_H_DIRECTORY_UPDATE.CLEAR

Directory Updates; Directory Clear

UNC_H_DIRECTORY_UPDATE.SET

Directory Updates; Directory Set

UNC_H_HITME_HIT.ACKCNFLTWBI

Counts Number of Hits in HitMe Cache; op is AckCnfltWbI

UNC_H_HITME_HIT.ALL

Counts Number of Hits in HitMe Cache; All Requests

UNC_H_HITME_HIT.ALLOCS

Counts Number of Hits in HitMe Cache; Allocations

UNC_H_HITME_HIT.EVICTS

Counts Number of Hits in HitMe Cache; Allocations

UNC_H_HITME_HIT.HOM

Counts Number of Hits in HitMe Cache; HOM Requests

UNC_H_HITME_HIT.INVALS

Counts Number of Hits in HitMe Cache; Invalidations

UNC_H_HITME_HIT.READ_OR_INVITOE

Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE

UNC_H_HITME_HIT.RSP

Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI

UNC_H_HITME_HIT.RSPFWDI_LOCAL

Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request

UNC_H_HITME_HIT.RSPFWDI_REMOTE

Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request

UNC_H_HITME_HIT.RSPFWDS

Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb

UNC_H_HITME_HIT.WBMTOE_OR_S

Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS

UNC_H_HITME_HIT.WBMTOI

Counts Number of Hits in HitMe Cache; op is WbMtoI

UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI

Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI

UNC_H_HITME_HIT_PV_BITS_SET.ALL

Accumulates Number of PV bits set on HitMe Cache Hits; All Requests

UNC_H_HITME_HIT_PV_BITS_SET.HOM

Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests

UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE

Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE

UNC_H_HITME_HIT_PV_BITS_SET.RSP

Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI

UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL

Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request

UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE

Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request

UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS

Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb

UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S

Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS

UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI

Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI

UNC_H_HITME_LOOKUP.ACKCNFLTWBI

Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI

UNC_H_HITME_LOOKUP.ALL

Counts Number of times HitMe Cache is accessed; All Requests

UNC_H_HITME_LOOKUP.ALLOCS

Counts Number of times HitMe Cache is accessed; Allocations

UNC_H_HITME_LOOKUP.HOM

Counts Number of times HitMe Cache is accessed; HOM Requests

UNC_H_HITME_LOOKUP.INVALS

Counts Number of times HitMe Cache is accessed; Invalidations

UNC_H_HITME_LOOKUP.READ_OR_INVITOE

Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE

UNC_H_HITME_LOOKUP.RSP

Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI

UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL

Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request

UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE

Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request

UNC_H_HITME_LOOKUP.RSPFWDS

Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb

UNC_H_HITME_LOOKUP.WBMTOE_OR_S

Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS

UNC_H_HITME_LOOKUP.WBMTOI

Counts Number of times HitMe Cache is accessed; op is WbMtoI

UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0

Cycles without QPI Ingress Credits; AD to QPI Link 0

UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1

Cycles without QPI Ingress Credits; AD to QPI Link 1

UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2

Cycles without QPI Ingress Credits; BL to QPI Link 0

UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0

Cycles without QPI Ingress Credits; BL to QPI Link 0

UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1

Cycles without QPI Ingress Credits; BL to QPI Link 1

UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2

Cycles without QPI Ingress Credits; BL to QPI Link 1

UNC_H_IMC_READS.NORMAL

HA to iMC Normal Priority Reads Issued; Normal Priority

UNC_H_IMC_RETRY

Retry Events

UNC_H_IMC_WRITES.ALL

HA to iMC Full Line Writes Issued; All Writes

UNC_H_IMC_WRITES.FULL

HA to iMC Full Line Writes Issued; Full Line Non-ISOCH

UNC_H_IMC_WRITES.FULL_ISOCH

HA to iMC Full Line Writes Issued; ISOCH Full Line

UNC_H_IMC_WRITES.PARTIAL

HA to iMC Full Line Writes Issued; Partial Non-ISOCH

UNC_H_IMC_WRITES.PARTIAL_ISOCH

HA to iMC Full Line Writes Issued; ISOCH Partial

UNC_H_IOT_BACKPRESSURE.HUB

IOT Backpressure

UNC_H_IOT_BACKPRESSURE.SAT

IOT Backpressure

UNC_H_IOT_CTS_EAST_LO.CTS0

IOT Common Trigger Sequencer - Lo

UNC_H_IOT_CTS_EAST_LO.CTS1

IOT Common Trigger Sequencer - Lo

UNC_H_IOT_CTS_HI.CTS2

IOT Common Trigger Sequencer - Hi

UNC_H_IOT_CTS_HI.CTS3

IOT Common Trigger Sequencer - Hi

UNC_H_IOT_CTS_WEST_LO.CTS0

IOT Common Trigger Sequencer - Lo

UNC_H_IOT_CTS_WEST_LO.CTS1

IOT Common Trigger Sequencer - Lo

UNC_H_OSB.CANCELLED

OSB Snoop Broadcast; Cancelled

UNC_H_OSB.INVITOE_LOCAL

OSB Snoop Broadcast; Local InvItoE

UNC_H_OSB.READS_LOCAL

OSB Snoop Broadcast; Local Reads

UNC_H_OSB.READS_LOCAL_USEFUL

OSB Snoop Broadcast; Reads Local - Useful

UNC_H_OSB.REMOTE

OSB Snoop Broadcast; Remote

UNC_H_OSB.REMOTE_USEFUL

OSB Snoop Broadcast; Remote - Useful

UNC_H_OSB_EDR.ALL

OSB Early Data Return; All

UNC_H_OSB_EDR.READS_LOCAL_I

OSB Early Data Return; Reads to Local I

UNC_H_OSB_EDR.READS_LOCAL_S

OSB Early Data Return; Reads to Local S

UNC_H_OSB_EDR.READS_REMOTE_I

OSB Early Data Return; Reads to Remote I

UNC_H_OSB_EDR.READS_REMOTE_S

OSB Early Data Return; Reads to Remote S

UNC_H_REQUESTS.INVITOE_LOCAL

Read and Write Requests; Local InvItoEs

UNC_H_REQUESTS.INVITOE_REMOTE

Read and Write Requests; Remote InvItoEs

UNC_H_REQUESTS.READS

Read and Write Requests; Reads

UNC_H_REQUESTS.READS_LOCAL

Read and Write Requests; Local Reads

UNC_H_REQUESTS.READS_REMOTE

Read and Write Requests; Remote Reads

UNC_H_REQUESTS.WRITES

Read and Write Requests; Writes

UNC_H_REQUESTS.WRITES_LOCAL

Read and Write Requests; Local Writes

UNC_H_REQUESTS.WRITES_REMOTE

Read and Write Requests; Remote Writes

UNC_H_RING_AD_USED.CCW

HA AD Ring in Use; Counterclockwise

UNC_H_RING_AD_USED.CCW_EVEN

HA AD Ring in Use; Counterclockwise and Even

UNC_H_RING_AD_USED.CCW_ODD

HA AD Ring in Use; Counterclockwise and Odd

UNC_H_RING_AD_USED.CW

HA AD Ring in Use; Clockwise

UNC_H_RING_AD_USED.CW_EVEN

HA AD Ring in Use; Clockwise and Even

UNC_H_RING_AD_USED.CW_ODD

HA AD Ring in Use; Clockwise and Odd

UNC_H_RING_AK_USED.ALL

HA AK Ring in Use; All

UNC_H_RING_AK_USED.CCW

HA AK Ring in Use; Counterclockwise

UNC_H_RING_AK_USED.CCW_EVEN

HA AK Ring in Use; Counterclockwise and Even

UNC_H_RING_AK_USED.CCW_ODD

HA AK Ring in Use; Counterclockwise and Odd

UNC_H_RING_AK_USED.CW

HA AK Ring in Use; Clockwise

UNC_H_RING_AK_USED.CW_EVEN

HA AK Ring in Use; Clockwise and Even

UNC_H_RING_AK_USED.CW_ODD

HA AK Ring in Use; Clockwise and Odd

UNC_H_RING_BL_USED.ALL

HA BL Ring in Use; All

UNC_H_RING_BL_USED.CCW

HA BL Ring in Use; Counterclockwise

UNC_H_RING_BL_USED.CCW_EVEN

HA BL Ring in Use; Counterclockwise and Even

UNC_H_RING_BL_USED.CCW_ODD

HA BL Ring in Use; Counterclockwise and Odd

UNC_H_RING_BL_USED.CW

HA BL Ring in Use; Clockwise

UNC_H_RING_BL_USED.CW_EVEN

HA BL Ring in Use; Clockwise and Even

UNC_H_RING_BL_USED.CW_ODD

HA BL Ring in Use; Clockwise and Odd

UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0

iMC RPQ Credits Empty - Regular; Channel 0

UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1

iMC RPQ Credits Empty - Regular; Channel 1

UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2

iMC RPQ Credits Empty - Regular; Channel 2

UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3

iMC RPQ Credits Empty - Regular; Channel 3

UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0

iMC RPQ Credits Empty - Special; Channel 0

UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1

iMC RPQ Credits Empty - Special; Channel 1

UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2

iMC RPQ Credits Empty - Special; Channel 2

UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3

iMC RPQ Credits Empty - Special; Channel 3

UNC_H_SBO0_CREDITS_ACQUIRED.AD

SBo0 Credits Acquired; For AD Ring

UNC_H_SBO0_CREDITS_ACQUIRED.BL

SBo0 Credits Acquired; For BL Ring

UNC_H_SBO0_CREDIT_OCCUPANCY.AD

SBo0 Credits Occupancy; For AD Ring

UNC_H_SBO0_CREDIT_OCCUPANCY.BL

SBo0 Credits Occupancy; For BL Ring

UNC_H_SBO1_CREDITS_ACQUIRED.AD

SBo1 Credits Acquired; For AD Ring

UNC_H_SBO1_CREDITS_ACQUIRED.BL

SBo1 Credits Acquired; For BL Ring

UNC_H_SBO1_CREDIT_OCCUPANCY.AD

SBo1 Credits Occupancy; For AD Ring

UNC_H_SBO1_CREDIT_OCCUPANCY.BL

SBo1 Credits Occupancy; For BL Ring

UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL

Data beat the Snoop Responses; Local Requests

UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE

Data beat the Snoop Responses; Remote Requests

UNC_H_SNOOP_CYCLES_NE.ALL

Cycles with Snoops Outstanding; All Requests

UNC_H_SNOOP_CYCLES_NE.LOCAL

Cycles with Snoops Outstanding; Local Requests

UNC_H_SNOOP_CYCLES_NE.REMOTE

Cycles with Snoops Outstanding; Remote Requests

UNC_H_SNOOP_OCCUPANCY.LOCAL

Tracker Snoops Outstanding Accumulator; Local Requests

UNC_H_SNOOP_OCCUPANCY.REMOTE

Tracker Snoops Outstanding Accumulator; Remote Requests

UNC_H_SNOOP_RESP.RSPCNFLCT

Snoop Responses Received; RSPCNFLCT*

UNC_H_SNOOP_RESP.RSPI

Snoop Responses Received; RspI

UNC_H_SNOOP_RESP.RSPIFWD

Snoop Responses Received; RspIFwd

UNC_H_SNOOP_RESP.RSPS

Snoop Responses Received; RspS

UNC_H_SNOOP_RESP.RSPSFWD

Snoop Responses Received; RspSFwd

UNC_H_SNOOP_RESP.RSP_FWD_WB

Snoop Responses Received; Rsp*Fwd*WB

UNC_H_SNOOP_RESP.RSP_WB

Snoop Responses Received; Rsp*WB

UNC_H_SNP_RESP_RECV_LOCAL.OTHER

Snoop Responses Received Local; Other

UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT

Snoop Responses Received Local; RspCnflct

UNC_H_SNP_RESP_RECV_LOCAL.RSPI

Snoop Responses Received Local; RspI

UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD

Snoop Responses Received Local; RspIFwd

UNC_H_SNP_RESP_RECV_LOCAL.RSPS

Snoop Responses Received Local; RspS

UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD

Snoop Responses Received Local; RspSFwd

UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB

Snoop Responses Received Local; Rsp*FWD*WB

UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB

Snoop Responses Received Local; Rsp*WB

UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD

Stall on No Sbo Credits; For SBo0, AD Ring

UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL

Stall on No Sbo Credits; For SBo0, BL Ring

UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD

Stall on No Sbo Credits; For SBo1, AD Ring

UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL

Stall on No Sbo Credits; For SBo1, BL Ring

UNC_H_TAD_REQUESTS_G0.REGION0

HA Requests to a TAD Region - Group 0; TAD Region 0

UNC_H_TAD_REQUESTS_G0.REGION1

HA Requests to a TAD Region - Group 0; TAD Region 1

UNC_H_TAD_REQUESTS_G0.REGION2

HA Requests to a TAD Region - Group 0; TAD Region 2

UNC_H_TAD_REQUESTS_G0.REGION3

HA Requests to a TAD Region - Group 0; TAD Region 3

UNC_H_TAD_REQUESTS_G0.REGION4

HA Requests to a TAD Region - Group 0; TAD Region 4

UNC_H_TAD_REQUESTS_G0.REGION5

HA Requests to a TAD Region - Group 0; TAD Region 5

UNC_H_TAD_REQUESTS_G0.REGION6

HA Requests to a TAD Region - Group 0; TAD Region 6

UNC_H_TAD_REQUESTS_G0.REGION7

HA Requests to a TAD Region - Group 0; TAD Region 7

UNC_H_TAD_REQUESTS_G1.REGION10

HA Requests to a TAD Region - Group 1; TAD Region 10

UNC_H_TAD_REQUESTS_G1.REGION11

HA Requests to a TAD Region - Group 1; TAD Region 11

UNC_H_TAD_REQUESTS_G1.REGION8

HA Requests to a TAD Region - Group 1; TAD Region 8

UNC_H_TAD_REQUESTS_G1.REGION9

HA Requests to a TAD Region - Group 1; TAD Region 9

UNC_H_TRACKER_CYCLES_FULL.ALL

Tracker Cycles Full; Cycles Completely Used

UNC_H_TRACKER_CYCLES_FULL.GP

Tracker Cycles Full; Cycles GP Completely Used

UNC_H_TRACKER_CYCLES_NE.ALL

Tracker Cycles Not Empty; All Requests

UNC_H_TRACKER_CYCLES_NE.LOCAL

Tracker Cycles Not Empty; Local Requests

UNC_H_TRACKER_CYCLES_NE.REMOTE

Tracker Cycles Not Empty; Remote Requests

UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL

Tracker Occupancy Accumultor; Local InvItoE Requests

UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE

Tracker Occupancy Accumultor; Remote InvItoE Requests

UNC_H_TRACKER_OCCUPANCY.READS_LOCAL

Tracker Occupancy Accumultor; Local Read Requests

UNC_H_TRACKER_OCCUPANCY.READS_REMOTE

Tracker Occupancy Accumultor; Remote Read Requests

UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL

Tracker Occupancy Accumultor; Local Write Requests

UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE

Tracker Occupancy Accumultor; Remote Write Requests

UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL

Data Pending Occupancy Accumultor; Local Requests

UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE

Data Pending Occupancy Accumultor; Remote Requests

UNC_H_TxR_AD.HOM

Outbound NDR Ring Transactions; Non-data Responses

UNC_H_TxR_AD_CYCLES_FULL.ALL

AD Egress Full; All

UNC_H_TxR_AD_CYCLES_FULL.SCHED0

AD Egress Full; Scheduler 0

UNC_H_TxR_AD_CYCLES_FULL.SCHED1

AD Egress Full; Scheduler 1

UNC_H_TxR_AD_CYCLES_NE.ALL

AD Egress Not Empty; All

UNC_H_TxR_AD_CYCLES_NE.SCHED0

AD Egress Not Empty; Scheduler 0

UNC_H_TxR_AD_CYCLES_NE.SCHED1

AD Egress Not Empty; Scheduler 1

UNC_H_TxR_AD_INSERTS.ALL

AD Egress Allocations; All

UNC_H_TxR_AD_INSERTS.SCHED0

AD Egress Allocations; Scheduler 0

UNC_H_TxR_AD_INSERTS.SCHED1

AD Egress Allocations; Scheduler 1

UNC_H_TxR_AK_CYCLES_FULL.ALL

AK Egress Full; All

UNC_H_TxR_AK_CYCLES_FULL.SCHED0

AK Egress Full; Scheduler 0

UNC_H_TxR_AK_CYCLES_FULL.SCHED1

AK Egress Full; Scheduler 1

UNC_H_TxR_AK_CYCLES_NE.ALL

AK Egress Not Empty; All

UNC_H_TxR_AK_CYCLES_NE.SCHED0

AK Egress Not Empty; Scheduler 0

UNC_H_TxR_AK_CYCLES_NE.SCHED1

AK Egress Not Empty; Scheduler 1

UNC_H_TxR_AK_INSERTS.ALL

AK Egress Allocations; All

UNC_H_TxR_AK_INSERTS.SCHED0

AK Egress Allocations; Scheduler 0

UNC_H_TxR_AK_INSERTS.SCHED1

AK Egress Allocations; Scheduler 1

UNC_H_TxR_BL.DRS_CACHE

Outbound DRS Ring Transactions to Cache; Data to Cache

UNC_H_TxR_BL.DRS_CORE

Outbound DRS Ring Transactions to Cache; Data to Core

UNC_H_TxR_BL.DRS_QPI

Outbound DRS Ring Transactions to Cache; Data to QPI

UNC_H_TxR_BL_CYCLES_FULL.ALL

BL Egress Full; All

UNC_H_TxR_BL_CYCLES_FULL.SCHED0

BL Egress Full; Scheduler 0

UNC_H_TxR_BL_CYCLES_FULL.SCHED1

BL Egress Full; Scheduler 1

UNC_H_TxR_BL_CYCLES_NE.ALL

BL Egress Not Empty; All

UNC_H_TxR_BL_CYCLES_NE.SCHED0

BL Egress Not Empty; Scheduler 0

UNC_H_TxR_BL_CYCLES_NE.SCHED1

BL Egress Not Empty; Scheduler 1

UNC_H_TxR_BL_INSERTS.ALL

BL Egress Allocations; All

UNC_H_TxR_BL_INSERTS.SCHED0

BL Egress Allocations; Scheduler 0

UNC_H_TxR_BL_INSERTS.SCHED1

BL Egress Allocations; Scheduler 1

UNC_H_TxR_STARVED.AK

Injection Starvation; For AK Ring

UNC_H_TxR_STARVED.BL

Injection Starvation; For BL Ring

UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0

HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0

UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1

HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1

UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2

HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2

UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3

HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3

UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0

HA iMC CHN0 WPQ Credits Empty - Special; Channel 0

UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1

HA iMC CHN0 WPQ Credits Empty - Special; Channel 1

UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2

HA iMC CHN0 WPQ Credits Empty - Special; Channel 2

UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3

HA iMC CHN0 WPQ Credits Empty - Special; Channel 3

UNC_I_CACHE_TOTAL_OCCUPANCY.ANY

Total Write Cache Occupancy; Any Source

UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE

Total Write Cache Occupancy; Select Source

UNC_I_CLOCKTICKS

Clocks in the IRP

UNC_I_COHERENT_OPS.CLFLUSH

Coherent Ops; CLFlush

UNC_I_COHERENT_OPS.CRD

Coherent Ops; CRd

UNC_I_COHERENT_OPS.DRD

Coherent Ops; DRd

UNC_I_COHERENT_OPS.PCIDCAHINT

Coherent Ops; PCIDCAHin5t

UNC_I_COHERENT_OPS.PCIRDCUR

Coherent Ops; PCIRdCur

UNC_I_COHERENT_OPS.PCITOM

Coherent Ops; PCIItoM

UNC_I_COHERENT_OPS.RFO

Coherent Ops; RFO

UNC_I_COHERENT_OPS.WBMTOI

Coherent Ops; WbMtoI

UNC_I_MISC0.2ND_ATOMIC_INSERT

Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary

UNC_I_MISC0.2ND_RD_INSERT

Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary

UNC_I_MISC0.2ND_WR_INSERT

Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary

UNC_I_MISC0.FAST_REJ

Misc Events - Set 0; Fastpath Rejects

UNC_I_MISC0.FAST_REQ

Misc Events - Set 0; Fastpath Requests

UNC_I_MISC0.FAST_XFER

Misc Events - Set 0; Fastpath Transfers From Primary to Secondary

UNC_I_MISC0.PF_ACK_HINT

Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary

UNC_I_MISC0.PF_TIMEOUT

Misc Events - Set 0; Prefetch TimeOut

UNC_I_MISC1.DATA_THROTTLE

Misc Events - Set 1; Data Throttled

UNC_I_MISC1.LOST_FWD

Misc Events - Set 1

UNC_I_MISC1.SEC_RCVD_INVLD

Misc Events - Set 1; Received Invalid

UNC_I_MISC1.SEC_RCVD_VLD

Misc Events - Set 1; Received Valid

UNC_I_MISC1.SLOW_E

Misc Events - Set 1; Slow Transfer of E Line

UNC_I_MISC1.SLOW_I

Misc Events - Set 1; Slow Transfer of I Line

UNC_I_MISC1.SLOW_M

Misc Events - Set 1; Slow Transfer of M Line

UNC_I_MISC1.SLOW_S

Misc Events - Set 1; Slow Transfer of S Line

UNC_I_RxR_AK_INSERTS

AK Ingress Occupancy

UNC_I_RxR_BL_DRS_CYCLES_FULL

tbd

UNC_I_RxR_BL_DRS_INSERTS

BL Ingress Occupancy - DRS

UNC_I_RxR_BL_DRS_OCCUPANCY

tbd

UNC_I_RxR_BL_NCB_CYCLES_FULL

tbd

UNC_I_RxR_BL_NCB_INSERTS

BL Ingress Occupancy - NCB

UNC_I_RxR_BL_NCB_OCCUPANCY

tbd

UNC_I_RxR_BL_NCS_CYCLES_FULL

tbd

UNC_I_RxR_BL_NCS_INSERTS

BL Ingress Occupancy - NCS

UNC_I_RxR_BL_NCS_OCCUPANCY

tbd

UNC_I_SNOOP_RESP.HIT_ES

Snoop Responses; Hit E or S

UNC_I_SNOOP_RESP.HIT_I

Snoop Responses; Hit I

UNC_I_SNOOP_RESP.HIT_M

Snoop Responses; Hit M

UNC_I_SNOOP_RESP.MISS

Snoop Responses; Miss

UNC_I_SNOOP_RESP.SNPCODE

Snoop Responses; SnpCode

UNC_I_SNOOP_RESP.SNPDATA

Snoop Responses; SnpData

UNC_I_SNOOP_RESP.SNPINV

Snoop Responses; SnpInv

UNC_I_TRANSACTIONS.ATOMIC

Inbound Transaction Count; Atomic

UNC_I_TRANSACTIONS.ORDERINGQ

Inbound Transaction Count; Select Source

UNC_I_TRANSACTIONS.OTHER

Inbound Transaction Count; Other

UNC_I_TRANSACTIONS.RD_PREF

Inbound Transaction Count; Read Prefetches

UNC_I_TRANSACTIONS.READS

Inbound Transaction Count; Reads

UNC_I_TRANSACTIONS.WRITES

Inbound Transaction Count; Writes

UNC_I_TRANSACTIONS.WR_PREF

Inbound Transaction Count; Write Prefetches

UNC_I_TxR_AD_STALL_CREDIT_CYCLES

No AD Egress Credit Stalls

UNC_I_TxR_BL_STALL_CREDIT_CYCLES

No BL Egress Credit Stalls

UNC_I_TxR_DATA_INSERTS_NCB

Outbound Read Requests

UNC_I_TxR_DATA_INSERTS_NCS

Outbound Read Requests

UNC_I_TxR_REQUEST_OCCUPANCY

Outbound Request Queue Occupancy

UNC_M_ACT_COUNT.BYP

DRAM Activate Count; Activate due to Write

UNC_M_ACT_COUNT.RD

DRAM Activate Count; Activate due to Read

UNC_M_ACT_COUNT.WR

DRAM Activate Count; Activate due to Write

UNC_M_BYP_CMDS.ACT

ACT command issued by 2 cycle bypass

UNC_M_BYP_CMDS.CAS

CAS command issued by 2 cycle bypass

UNC_M_BYP_CMDS.PRE

PRE command issued by 2 cycle bypass

UNC_M_CAS_COUNT.ALL

DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)

UNC_M_CAS_COUNT.RD

DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)

UNC_M_CAS_COUNT.RD_REG

DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)

UNC_M_CAS_COUNT.RD_RMM

DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM

UNC_M_CAS_COUNT.RD_UNDERFILL

DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued

UNC_M_CAS_COUNT.RD_WMM

DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM

UNC_M_CAS_COUNT.WR

DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)

UNC_M_CAS_COUNT.WR_RMM

DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode

UNC_M_CAS_COUNT.WR_WMM

DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode

UNC_M_CLOCKTICKS

DRAM Clockticks. This is an alias of the UNC_M_DCLOCKTICKS event.

UNC_M_DCLOCKTICKS

DRAM Clockticks

UNC_M_DRAM_PRE_ALL

DRAM Precharge All Commands

UNC_M_DRAM_REFRESH.HIGH

Number of DRAM Refreshes Issued

UNC_M_DRAM_REFRESH.PANIC

Number of DRAM Refreshes Issued

UNC_M_ECC_CORRECTABLE_ERRORS

ECC Correctable Errors

UNC_M_MAJOR_MODES.ISOCH

Cycles in a Major Mode; Isoch Major Mode

UNC_M_MAJOR_MODES.PARTIAL

Cycles in a Major Mode; Partial Major Mode

UNC_M_MAJOR_MODES.READ

Cycles in a Major Mode; Read Major Mode

UNC_M_MAJOR_MODES.WRITE

Cycles in a Major Mode; Write Major Mode

UNC_M_POWER_CHANNEL_DLLOFF

Channel DLLOFF Cycles

UNC_M_POWER_CHANNEL_PPD

Channel PPD Cycles

UNC_M_POWER_CKE_CYCLES.RANK0

CKE_ON_CYCLES by Rank; DIMM ID

UNC_M_POWER_CKE_CYCLES.RANK1

CKE_ON_CYCLES by Rank; DIMM ID

UNC_M_POWER_CKE_CYCLES.RANK2

CKE_ON_CYCLES by Rank; DIMM ID

UNC_M_POWER_CKE_CYCLES.RANK3

CKE_ON_CYCLES by Rank; DIMM ID

UNC_M_POWER_CKE_CYCLES.RANK4

CKE_ON_CYCLES by Rank; DIMM ID

UNC_M_POWER_CKE_CYCLES.RANK5

CKE_ON_CYCLES by Rank; DIMM ID

UNC_M_POWER_CKE_CYCLES.RANK6

CKE_ON_CYCLES by Rank; DIMM ID

UNC_M_POWER_CKE_CYCLES.RANK7

CKE_ON_CYCLES by Rank; DIMM ID

UNC_M_POWER_CRITICAL_THROTTLE_CYCLES

Critical Throttle Cycles

UNC_M_POWER_PCU_THROTTLING

tbd

UNC_M_POWER_SELF_REFRESH

Clock-Enabled Self-Refresh

UNC_M_POWER_THROTTLE_CYCLES.RANK0

Throttle Cycles for Rank 0; DIMM ID

UNC_M_POWER_THROTTLE_CYCLES.RANK1

Throttle Cycles for Rank 0; DIMM ID

UNC_M_POWER_THROTTLE_CYCLES.RANK2

Throttle Cycles for Rank 0; DIMM ID

UNC_M_POWER_THROTTLE_CYCLES.RANK3

Throttle Cycles for Rank 0; DIMM ID

UNC_M_POWER_THROTTLE_CYCLES.RANK4

Throttle Cycles for Rank 0; DIMM ID

UNC_M_POWER_THROTTLE_CYCLES.RANK5

Throttle Cycles for Rank 0; DIMM ID

UNC_M_POWER_THROTTLE_CYCLES.RANK6

Throttle Cycles for Rank 0; DIMM ID

UNC_M_POWER_THROTTLE_CYCLES.RANK7

Throttle Cycles for Rank 0; DIMM ID

UNC_M_PREEMPTION.RD_PREEMPT_RD

Read Preemption Count; Read over Read Preemption

UNC_M_PREEMPTION.RD_PREEMPT_WR

Read Preemption Count; Read over Write Preemption

UNC_M_PRE_COUNT.BYP

DRAM Precharge commands.; Precharge due to bypass

UNC_M_PRE_COUNT.PAGE_CLOSE

DRAM Precharge commands.; Precharge due to timer expiration

UNC_M_PRE_COUNT.PAGE_MISS

DRAM Precharge commands.; Precharges due to page miss

UNC_M_PRE_COUNT.RD

DRAM Precharge commands.; Precharge due to read

UNC_M_PRE_COUNT.WR

DRAM Precharge commands.; Precharge due to write

UNC_M_RD_CAS_PRIO.HIGH

Read CAS issued with HIGH priority

UNC_M_RD_CAS_PRIO.LOW

Read CAS issued with LOW priority

UNC_M_RD_CAS_PRIO.MED

Read CAS issued with MEDIUM priority

UNC_M_RD_CAS_PRIO.PANIC

Read CAS issued with PANIC NON ISOCH priority (starved)

UNC_M_RD_CAS_RANK0.ALLBANKS

RD_CAS Access to Rank 0; All Banks

UNC_M_RD_CAS_RANK0.BANK0

RD_CAS Access to Rank 0; Bank 0

UNC_M_RD_CAS_RANK0.BANK1

RD_CAS Access to Rank 0; Bank 1

UNC_M_RD_CAS_RANK0.BANK10

RD_CAS Access to Rank 0; Bank 10

UNC_M_RD_CAS_RANK0.BANK11

RD_CAS Access to Rank 0; Bank 11

UNC_M_RD_CAS_RANK0.BANK12

RD_CAS Access to Rank 0; Bank 12

UNC_M_RD_CAS_RANK0.BANK13

RD_CAS Access to Rank 0; Bank 13

UNC_M_RD_CAS_RANK0.BANK14

RD_CAS Access to Rank 0; Bank 14

UNC_M_RD_CAS_RANK0.BANK15

RD_CAS Access to Rank 0; Bank 15

UNC_M_RD_CAS_RANK0.BANK2

RD_CAS Access to Rank 0; Bank 2

UNC_M_RD_CAS_RANK0.BANK3

RD_CAS Access to Rank 0; Bank 3

UNC_M_RD_CAS_RANK0.BANK4

RD_CAS Access to Rank 0; Bank 4

UNC_M_RD_CAS_RANK0.BANK5

RD_CAS Access to Rank 0; Bank 5

UNC_M_RD_CAS_RANK0.BANK6

RD_CAS Access to Rank 0; Bank 6

UNC_M_RD_CAS_RANK0.BANK7

RD_CAS Access to Rank 0; Bank 7

UNC_M_RD_CAS_RANK0.BANK8

RD_CAS Access to Rank 0; Bank 8

UNC_M_RD_CAS_RANK0.BANK9

RD_CAS Access to Rank 0; Bank 9

UNC_M_RD_CAS_RANK0.BANKG0

RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)

UNC_M_RD_CAS_RANK0.BANKG1

RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)

UNC_M_RD_CAS_RANK0.BANKG2

RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)

UNC_M_RD_CAS_RANK0.BANKG3

RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)

UNC_M_RD_CAS_RANK1.ALLBANKS

RD_CAS Access to Rank 1; All Banks

UNC_M_RD_CAS_RANK1.BANK0

RD_CAS Access to Rank 1; Bank 0

UNC_M_RD_CAS_RANK1.BANK1

RD_CAS Access to Rank 1; Bank 1

UNC_M_RD_CAS_RANK1.BANK10

RD_CAS Access to Rank 1; Bank 10

UNC_M_RD_CAS_RANK1.BANK11

RD_CAS Access to Rank 1; Bank 11

UNC_M_RD_CAS_RANK1.BANK12

RD_CAS Access to Rank 1; Bank 12

UNC_M_RD_CAS_RANK1.BANK13

RD_CAS Access to Rank 1; Bank 13

UNC_M_RD_CAS_RANK1.BANK14

RD_CAS Access to Rank 1; Bank 14

UNC_M_RD_CAS_RANK1.BANK15

RD_CAS Access to Rank 1; Bank 15

UNC_M_RD_CAS_RANK1.BANK2

RD_CAS Access to Rank 1; Bank 2

UNC_M_RD_CAS_RANK1.BANK3

RD_CAS Access to Rank 1; Bank 3

UNC_M_RD_CAS_RANK1.BANK4

RD_CAS Access to Rank 1; Bank 4

UNC_M_RD_CAS_RANK1.BANK5

RD_CAS Access to Rank 1; Bank 5

UNC_M_RD_CAS_RANK1.BANK6

RD_CAS Access to Rank 1; Bank 6

UNC_M_RD_CAS_RANK1.BANK7

RD_CAS Access to Rank 1; Bank 7

UNC_M_RD_CAS_RANK1.BANK8

RD_CAS Access to Rank 1; Bank 8

UNC_M_RD_CAS_RANK1.BANK9

RD_CAS Access to Rank 1; Bank 9

UNC_M_RD_CAS_RANK1.BANKG0

RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)

UNC_M_RD_CAS_RANK1.BANKG1

RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)

UNC_M_RD_CAS_RANK1.BANKG2

RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)

UNC_M_RD_CAS_RANK1.BANKG3

RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)

UNC_M_RD_CAS_RANK2.BANK0

RD_CAS Access to Rank 2; Bank 0

UNC_M_RD_CAS_RANK4.ALLBANKS

RD_CAS Access to Rank 4; All Banks

UNC_M_RD_CAS_RANK4.BANK0

RD_CAS Access to Rank 4; Bank 0

UNC_M_RD_CAS_RANK4.BANK1

RD_CAS Access to Rank 4; Bank 1

UNC_M_RD_CAS_RANK4.BANK10

RD_CAS Access to Rank 4; Bank 10

UNC_M_RD_CAS_RANK4.BANK11

RD_CAS Access to Rank 4; Bank 11

UNC_M_RD_CAS_RANK4.BANK12

RD_CAS Access to Rank 4; Bank 12

UNC_M_RD_CAS_RANK4.BANK13

RD_CAS Access to Rank 4; Bank 13

UNC_M_RD_CAS_RANK4.BANK14

RD_CAS Access to Rank 4; Bank 14

UNC_M_RD_CAS_RANK4.BANK15

RD_CAS Access to Rank 4; Bank 15

UNC_M_RD_CAS_RANK4.BANK2

RD_CAS Access to Rank 4; Bank 2

UNC_M_RD_CAS_RANK4.BANK3

RD_CAS Access to Rank 4; Bank 3

UNC_M_RD_CAS_RANK4.BANK4

RD_CAS Access to Rank 4; Bank 4

UNC_M_RD_CAS_RANK4.BANK5

RD_CAS Access to Rank 4; Bank 5

UNC_M_RD_CAS_RANK4.BANK6

RD_CAS Access to Rank 4; Bank 6

UNC_M_RD_CAS_RANK4.BANK7

RD_CAS Access to Rank 4; Bank 7

UNC_M_RD_CAS_RANK4.BANK8

RD_CAS Access to Rank 4; Bank 8

UNC_M_RD_CAS_RANK4.BANK9

RD_CAS Access to Rank 4; Bank 9

UNC_M_RD_CAS_RANK4.BANKG0

RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)

UNC_M_RD_CAS_RANK4.BANKG1

RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)

UNC_M_RD_CAS_RANK4.BANKG2

RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)

UNC_M_RD_CAS_RANK4.BANKG3

RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)

UNC_M_RD_CAS_RANK5.ALLBANKS

RD_CAS Access to Rank 5; All Banks

UNC_M_RD_CAS_RANK5.BANK0

RD_CAS Access to Rank 5; Bank 0

UNC_M_RD_CAS_RANK5.BANK1

RD_CAS Access to Rank 5; Bank 1

UNC_M_RD_CAS_RANK5.BANK10

RD_CAS Access to Rank 5; Bank 10

UNC_M_RD_CAS_RANK5.BANK11

RD_CAS Access to Rank 5; Bank 11

UNC_M_RD_CAS_RANK5.BANK12

RD_CAS Access to Rank 5; Bank 12

UNC_M_RD_CAS_RANK5.BANK13

RD_CAS Access to Rank 5; Bank 13

UNC_M_RD_CAS_RANK5.BANK14

RD_CAS Access to Rank 5; Bank 14

UNC_M_RD_CAS_RANK5.BANK15

RD_CAS Access to Rank 5; Bank 15

UNC_M_RD_CAS_RANK5.BANK2

RD_CAS Access to Rank 5; Bank 2

UNC_M_RD_CAS_RANK5.BANK3

RD_CAS Access to Rank 5; Bank 3

UNC_M_RD_CAS_RANK5.BANK4

RD_CAS Access to Rank 5; Bank 4

UNC_M_RD_CAS_RANK5.BANK5

RD_CAS Access to Rank 5; Bank 5

UNC_M_RD_CAS_RANK5.BANK6

RD_CAS Access to Rank 5; Bank 6

UNC_M_RD_CAS_RANK5.BANK7

RD_CAS Access to Rank 5; Bank 7

UNC_M_RD_CAS_RANK5.BANK8

RD_CAS Access to Rank 5; Bank 8

UNC_M_RD_CAS_RANK5.BANK9

RD_CAS Access to Rank 5; Bank 9

UNC_M_RD_CAS_RANK5.BANKG0

RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)

UNC_M_RD_CAS_RANK5.BANKG1

RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)

UNC_M_RD_CAS_RANK5.BANKG2

RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)

UNC_M_RD_CAS_RANK5.BANKG3

RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)

UNC_M_RD_CAS_RANK6.ALLBANKS

RD_CAS Access to Rank 6; All Banks

UNC_M_RD_CAS_RANK6.BANK0

RD_CAS Access to Rank 6; Bank 0

UNC_M_RD_CAS_RANK6.BANK1

RD_CAS Access to Rank 6; Bank 1

UNC_M_RD_CAS_RANK6.BANK10

RD_CAS Access to Rank 6; Bank 10

UNC_M_RD_CAS_RANK6.BANK11

RD_CAS Access to Rank 6; Bank 11

UNC_M_RD_CAS_RANK6.BANK12

RD_CAS Access to Rank 6; Bank 12

UNC_M_RD_CAS_RANK6.BANK13

RD_CAS Access to Rank 6; Bank 13

UNC_M_RD_CAS_RANK6.BANK14

RD_CAS Access to Rank 6; Bank 14

UNC_M_RD_CAS_RANK6.BANK15

RD_CAS Access to Rank 6; Bank 15

UNC_M_RD_CAS_RANK6.BANK2

RD_CAS Access to Rank 6; Bank 2

UNC_M_RD_CAS_RANK6.BANK3

RD_CAS Access to Rank 6; Bank 3

UNC_M_RD_CAS_RANK6.BANK4

RD_CAS Access to Rank 6; Bank 4

UNC_M_RD_CAS_RANK6.BANK5

RD_CAS Access to Rank 6; Bank 5

UNC_M_RD_CAS_RANK6.BANK6

RD_CAS Access to Rank 6; Bank 6

UNC_M_RD_CAS_RANK6.BANK7

RD_CAS Access to Rank 6; Bank 7

UNC_M_RD_CAS_RANK6.BANK8

RD_CAS Access to Rank 6; Bank 8

UNC_M_RD_CAS_RANK6.BANK9

RD_CAS Access to Rank 6; Bank 9

UNC_M_RD_CAS_RANK6.BANKG0

RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)

UNC_M_RD_CAS_RANK6.BANKG1

RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)

UNC_M_RD_CAS_RANK6.BANKG2

RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)

UNC_M_RD_CAS_RANK6.BANKG3

RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)

UNC_M_RD_CAS_RANK7.ALLBANKS

RD_CAS Access to Rank 7; All Banks

UNC_M_RD_CAS_RANK7.BANK0

RD_CAS Access to Rank 7; Bank 0

UNC_M_RD_CAS_RANK7.BANK1

RD_CAS Access to Rank 7; Bank 1

UNC_M_RD_CAS_RANK7.BANK10

RD_CAS Access to Rank 7; Bank 10

UNC_M_RD_CAS_RANK7.BANK11

RD_CAS Access to Rank 7; Bank 11

UNC_M_RD_CAS_RANK7.BANK12

RD_CAS Access to Rank 7; Bank 12

UNC_M_RD_CAS_RANK7.BANK13

RD_CAS Access to Rank 7; Bank 13

UNC_M_RD_CAS_RANK7.BANK14

RD_CAS Access to Rank 7; Bank 14

UNC_M_RD_CAS_RANK7.BANK15

RD_CAS Access to Rank 7; Bank 15

UNC_M_RD_CAS_RANK7.BANK2

RD_CAS Access to Rank 7; Bank 2

UNC_M_RD_CAS_RANK7.BANK3

RD_CAS Access to Rank 7; Bank 3

UNC_M_RD_CAS_RANK7.BANK4

RD_CAS Access to Rank 7; Bank 4

UNC_M_RD_CAS_RANK7.BANK5

RD_CAS Access to Rank 7; Bank 5

UNC_M_RD_CAS_RANK7.BANK6

RD_CAS Access to Rank 7; Bank 6

UNC_M_RD_CAS_RANK7.BANK7

RD_CAS Access to Rank 7; Bank 7

UNC_M_RD_CAS_RANK7.BANK8

RD_CAS Access to Rank 7; Bank 8

UNC_M_RD_CAS_RANK7.BANK9

RD_CAS Access to Rank 7; Bank 9

UNC_M_RD_CAS_RANK7.BANKG0

RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)

UNC_M_RD_CAS_RANK7.BANKG1

RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)

UNC_M_RD_CAS_RANK7.BANKG2

RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)

UNC_M_RD_CAS_RANK7.BANKG3

RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)

UNC_M_RPQ_CYCLES_NE

Read Pending Queue Not Empty

UNC_M_RPQ_INSERTS

Read Pending Queue Allocations

UNC_M_VMSE_MXB_WR_OCCUPANCY

VMSE MXB write buffer occupancy

UNC_M_VMSE_WR_PUSH.RMM

VMSE WR PUSH issued; VMSE write PUSH issued in RMM

UNC_M_VMSE_WR_PUSH.WMM

VMSE WR PUSH issued; VMSE write PUSH issued in WMM

UNC_M_WMM_TO_RMM.LOW_THRESH

Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter

UNC_M_WMM_TO_RMM.STARVE

Transition from WMM to RMM because of low threshold

UNC_M_WMM_TO_RMM.VMSE_RETRY

Transition from WMM to RMM because of low threshold

UNC_M_WPQ_CYCLES_FULL

Write Pending Queue Full Cycles

UNC_M_WPQ_CYCLES_NE

Write Pending Queue Not Empty

UNC_M_WPQ_READ_HIT

Write Pending Queue CAM Match

UNC_M_WPQ_WRITE_HIT

Write Pending Queue CAM Match

UNC_M_WRONG_MM

Not getting the requested Major Mode

UNC_M_WR_CAS_RANK0.ALLBANKS

WR_CAS Access to Rank 0; All Banks

UNC_M_WR_CAS_RANK0.BANK0

WR_CAS Access to Rank 0; Bank 0

UNC_M_WR_CAS_RANK0.BANK1

WR_CAS Access to Rank 0; Bank 1

UNC_M_WR_CAS_RANK0.BANK10

WR_CAS Access to Rank 0; Bank 10

UNC_M_WR_CAS_RANK0.BANK11

WR_CAS Access to Rank 0; Bank 11

UNC_M_WR_CAS_RANK0.BANK12

WR_CAS Access to Rank 0; Bank 12

UNC_M_WR_CAS_RANK0.BANK13

WR_CAS Access to Rank 0; Bank 13

UNC_M_WR_CAS_RANK0.BANK14

WR_CAS Access to Rank 0; Bank 14

UNC_M_WR_CAS_RANK0.BANK15

WR_CAS Access to Rank 0; Bank 15

UNC_M_WR_CAS_RANK0.BANK2

WR_CAS Access to Rank 0; Bank 2

UNC_M_WR_CAS_RANK0.BANK3

WR_CAS Access to Rank 0; Bank 3

UNC_M_WR_CAS_RANK0.BANK4

WR_CAS Access to Rank 0; Bank 4

UNC_M_WR_CAS_RANK0.BANK5

WR_CAS Access to Rank 0; Bank 5

UNC_M_WR_CAS_RANK0.BANK6

WR_CAS Access to Rank 0; Bank 6

UNC_M_WR_CAS_RANK0.BANK7

WR_CAS Access to Rank 0; Bank 7

UNC_M_WR_CAS_RANK0.BANK8

WR_CAS Access to Rank 0; Bank 8

UNC_M_WR_CAS_RANK0.BANK9

WR_CAS Access to Rank 0; Bank 9

UNC_M_WR_CAS_RANK0.BANKG0

WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)

UNC_M_WR_CAS_RANK0.BANKG1

WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)

UNC_M_WR_CAS_RANK0.BANKG2

WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)

UNC_M_WR_CAS_RANK0.BANKG3

WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)

UNC_M_WR_CAS_RANK1.ALLBANKS

WR_CAS Access to Rank 1; All Banks

UNC_M_WR_CAS_RANK1.BANK0

WR_CAS Access to Rank 1; Bank 0

UNC_M_WR_CAS_RANK1.BANK1

WR_CAS Access to Rank 1; Bank 1

UNC_M_WR_CAS_RANK1.BANK10

WR_CAS Access to Rank 1; Bank 10

UNC_M_WR_CAS_RANK1.BANK11

WR_CAS Access to Rank 1; Bank 11

UNC_M_WR_CAS_RANK1.BANK12

WR_CAS Access to Rank 1; Bank 12

UNC_M_WR_CAS_RANK1.BANK13

WR_CAS Access to Rank 1; Bank 13

UNC_M_WR_CAS_RANK1.BANK14

WR_CAS Access to Rank 1; Bank 14

UNC_M_WR_CAS_RANK1.BANK15

WR_CAS Access to Rank 1; Bank 15

UNC_M_WR_CAS_RANK1.BANK2

WR_CAS Access to Rank 1; Bank 2

UNC_M_WR_CAS_RANK1.BANK3

WR_CAS Access to Rank 1; Bank 3

UNC_M_WR_CAS_RANK1.BANK4

WR_CAS Access to Rank 1; Bank 4

UNC_M_WR_CAS_RANK1.BANK5

WR_CAS Access to Rank 1; Bank 5

UNC_M_WR_CAS_RANK1.BANK6

WR_CAS Access to Rank 1; Bank 6

UNC_M_WR_CAS_RANK1.BANK7

WR_CAS Access to Rank 1; Bank 7

UNC_M_WR_CAS_RANK1.BANK8

WR_CAS Access to Rank 1; Bank 8

UNC_M_WR_CAS_RANK1.BANK9

WR_CAS Access to Rank 1; Bank 9

UNC_M_WR_CAS_RANK1.BANKG0

WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)

UNC_M_WR_CAS_RANK1.BANKG1

WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)

UNC_M_WR_CAS_RANK1.BANKG2

WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)

UNC_M_WR_CAS_RANK1.BANKG3

WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)

UNC_M_WR_CAS_RANK4.ALLBANKS

WR_CAS Access to Rank 4; All Banks

UNC_M_WR_CAS_RANK4.BANK0

WR_CAS Access to Rank 4; Bank 0

UNC_M_WR_CAS_RANK4.BANK1

WR_CAS Access to Rank 4; Bank 1

UNC_M_WR_CAS_RANK4.BANK10

WR_CAS Access to Rank 4; Bank 10

UNC_M_WR_CAS_RANK4.BANK11

WR_CAS Access to Rank 4; Bank 11

UNC_M_WR_CAS_RANK4.BANK12

WR_CAS Access to Rank 4; Bank 12

UNC_M_WR_CAS_RANK4.BANK13

WR_CAS Access to Rank 4; Bank 13

UNC_M_WR_CAS_RANK4.BANK14

WR_CAS Access to Rank 4; Bank 14

UNC_M_WR_CAS_RANK4.BANK15

WR_CAS Access to Rank 4; Bank 15

UNC_M_WR_CAS_RANK4.BANK2

WR_CAS Access to Rank 4; Bank 2

UNC_M_WR_CAS_RANK4.BANK3

WR_CAS Access to Rank 4; Bank 3

UNC_M_WR_CAS_RANK4.BANK4

WR_CAS Access to Rank 4; Bank 4

UNC_M_WR_CAS_RANK4.BANK5

WR_CAS Access to Rank 4; Bank 5

UNC_M_WR_CAS_RANK4.BANK6

WR_CAS Access to Rank 4; Bank 6

UNC_M_WR_CAS_RANK4.BANK7

WR_CAS Access to Rank 4; Bank 7

UNC_M_WR_CAS_RANK4.BANK8

WR_CAS Access to Rank 4; Bank 8

UNC_M_WR_CAS_RANK4.BANK9

WR_CAS Access to Rank 4; Bank 9

UNC_M_WR_CAS_RANK4.BANKG0

WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)

UNC_M_WR_CAS_RANK4.BANKG1

WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)

UNC_M_WR_CAS_RANK4.BANKG2

WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)

UNC_M_WR_CAS_RANK4.BANKG3

WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)

UNC_M_WR_CAS_RANK5.ALLBANKS

WR_CAS Access to Rank 5; All Banks

UNC_M_WR_CAS_RANK5.BANK0

WR_CAS Access to Rank 5; Bank 0

UNC_M_WR_CAS_RANK5.BANK1

WR_CAS Access to Rank 5; Bank 1

UNC_M_WR_CAS_RANK5.BANK10

WR_CAS Access to Rank 5; Bank 10

UNC_M_WR_CAS_RANK5.BANK11

WR_CAS Access to Rank 5; Bank 11

UNC_M_WR_CAS_RANK5.BANK12

WR_CAS Access to Rank 5; Bank 12

UNC_M_WR_CAS_RANK5.BANK13

WR_CAS Access to Rank 5; Bank 13

UNC_M_WR_CAS_RANK5.BANK14

WR_CAS Access to Rank 5; Bank 14

UNC_M_WR_CAS_RANK5.BANK15

WR_CAS Access to Rank 5; Bank 15

UNC_M_WR_CAS_RANK5.BANK2

WR_CAS Access to Rank 5; Bank 2

UNC_M_WR_CAS_RANK5.BANK3

WR_CAS Access to Rank 5; Bank 3

UNC_M_WR_CAS_RANK5.BANK4

WR_CAS Access to Rank 5; Bank 4

UNC_M_WR_CAS_RANK5.BANK5

WR_CAS Access to Rank 5; Bank 5

UNC_M_WR_CAS_RANK5.BANK6

WR_CAS Access to Rank 5; Bank 6

UNC_M_WR_CAS_RANK5.BANK7

WR_CAS Access to Rank 5; Bank 7

UNC_M_WR_CAS_RANK5.BANK8

WR_CAS Access to Rank 5; Bank 8

UNC_M_WR_CAS_RANK5.BANK9

WR_CAS Access to Rank 5; Bank 9

UNC_M_WR_CAS_RANK5.BANKG0

WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)

UNC_M_WR_CAS_RANK5.BANKG1

WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)

UNC_M_WR_CAS_RANK5.BANKG2

WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)

UNC_M_WR_CAS_RANK5.BANKG3

WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)

UNC_M_WR_CAS_RANK6.ALLBANKS

WR_CAS Access to Rank 6; All Banks

UNC_M_WR_CAS_RANK6.BANK0

WR_CAS Access to Rank 6; Bank 0

UNC_M_WR_CAS_RANK6.BANK1

WR_CAS Access to Rank 6; Bank 1

UNC_M_WR_CAS_RANK6.BANK10

WR_CAS Access to Rank 6; Bank 10

UNC_M_WR_CAS_RANK6.BANK11

WR_CAS Access to Rank 6; Bank 11

UNC_M_WR_CAS_RANK6.BANK12

WR_CAS Access to Rank 6; Bank 12

UNC_M_WR_CAS_RANK6.BANK13

WR_CAS Access to Rank 6; Bank 13

UNC_M_WR_CAS_RANK6.BANK14

WR_CAS Access to Rank 6; Bank 14

UNC_M_WR_CAS_RANK6.BANK15

WR_CAS Access to Rank 6; Bank 15

UNC_M_WR_CAS_RANK6.BANK2

WR_CAS Access to Rank 6; Bank 2

UNC_M_WR_CAS_RANK6.BANK3

WR_CAS Access to Rank 6; Bank 3

UNC_M_WR_CAS_RANK6.BANK4

WR_CAS Access to Rank 6; Bank 4

UNC_M_WR_CAS_RANK6.BANK5

WR_CAS Access to Rank 6; Bank 5

UNC_M_WR_CAS_RANK6.BANK6

WR_CAS Access to Rank 6; Bank 6

UNC_M_WR_CAS_RANK6.BANK7

WR_CAS Access to Rank 6; Bank 7

UNC_M_WR_CAS_RANK6.BANK8

WR_CAS Access to Rank 6; Bank 8

UNC_M_WR_CAS_RANK6.BANK9

WR_CAS Access to Rank 6; Bank 9

UNC_M_WR_CAS_RANK6.BANKG0

WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)

UNC_M_WR_CAS_RANK6.BANKG1

WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)

UNC_M_WR_CAS_RANK6.BANKG2

WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)

UNC_M_WR_CAS_RANK6.BANKG3

WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)

UNC_M_WR_CAS_RANK7.ALLBANKS

WR_CAS Access to Rank 7; All Banks

UNC_M_WR_CAS_RANK7.BANK0

WR_CAS Access to Rank 7; Bank 0

UNC_M_WR_CAS_RANK7.BANK1

WR_CAS Access to Rank 7; Bank 1

UNC_M_WR_CAS_RANK7.BANK10

WR_CAS Access to Rank 7; Bank 10

UNC_M_WR_CAS_RANK7.BANK11

WR_CAS Access to Rank 7; Bank 11

UNC_M_WR_CAS_RANK7.BANK12

WR_CAS Access to Rank 7; Bank 12

UNC_M_WR_CAS_RANK7.BANK13

WR_CAS Access to Rank 7; Bank 13

UNC_M_WR_CAS_RANK7.BANK14

WR_CAS Access to Rank 7; Bank 14

UNC_M_WR_CAS_RANK7.BANK15

WR_CAS Access to Rank 7; Bank 15

UNC_M_WR_CAS_RANK7.BANK2

WR_CAS Access to Rank 7; Bank 2

UNC_M_WR_CAS_RANK7.BANK3

WR_CAS Access to Rank 7; Bank 3

UNC_M_WR_CAS_RANK7.BANK4

WR_CAS Access to Rank 7; Bank 4

UNC_M_WR_CAS_RANK7.BANK5

WR_CAS Access to Rank 7; Bank 5

UNC_M_WR_CAS_RANK7.BANK6

WR_CAS Access to Rank 7; Bank 6

UNC_M_WR_CAS_RANK7.BANK7

WR_CAS Access to Rank 7; Bank 7

UNC_M_WR_CAS_RANK7.BANK8

WR_CAS Access to Rank 7; Bank 8

UNC_M_WR_CAS_RANK7.BANK9

WR_CAS Access to Rank 7; Bank 9

UNC_M_WR_CAS_RANK7.BANKG0

WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)

UNC_M_WR_CAS_RANK7.BANKG1

WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)

UNC_M_WR_CAS_RANK7.BANKG2

WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)

UNC_M_WR_CAS_RANK7.BANKG3

WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)

UNC_P_CLOCKTICKS

pclk Cycles

UNC_P_CORE0_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE10_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE11_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE12_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE13_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE14_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE15_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE16_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE17_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE1_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE2_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE3_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE4_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE5_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE6_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE7_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE8_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_CORE9_TRANSITION_CYCLES

Core C State Transition Cycles

UNC_P_DEMOTIONS_CORE0

Core C State Demotions

UNC_P_DEMOTIONS_CORE1

Core C State Demotions

UNC_P_DEMOTIONS_CORE10

Core C State Demotions

UNC_P_DEMOTIONS_CORE11

Core C State Demotions

UNC_P_DEMOTIONS_CORE12

Core C State Demotions

UNC_P_DEMOTIONS_CORE13

Core C State Demotions

UNC_P_DEMOTIONS_CORE14

Core C State Demotions

UNC_P_DEMOTIONS_CORE15

Core C State Demotions

UNC_P_DEMOTIONS_CORE16

Core C State Demotions

UNC_P_DEMOTIONS_CORE17

Core C State Demotions

UNC_P_DEMOTIONS_CORE2

Core C State Demotions

UNC_P_DEMOTIONS_CORE3

Core C State Demotions

UNC_P_DEMOTIONS_CORE4

Core C State Demotions

UNC_P_DEMOTIONS_CORE5

Core C State Demotions

UNC_P_DEMOTIONS_CORE6

Core C State Demotions

UNC_P_DEMOTIONS_CORE7

Core C State Demotions

UNC_P_DEMOTIONS_CORE8

Core C State Demotions

UNC_P_DEMOTIONS_CORE9

Core C State Demotions

UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES

Thermal Strongest Upper Limit Cycles

UNC_P_FREQ_MAX_OS_CYCLES

OS Strongest Upper Limit Cycles

UNC_P_FREQ_MAX_POWER_CYCLES

Power Strongest Upper Limit Cycles

UNC_P_FREQ_MIN_IO_P_CYCLES

IO P Limit Strongest Lower Limit Cycles

UNC_P_FREQ_TRANS_CYCLES

Cycles spent changing Frequency

UNC_P_MEMORY_PHASE_SHEDDING_CYCLES

Memory Phase Shedding Cycles

UNC_P_PKG_RESIDENCY_C0_CYCLES

Package C State Residency - C0

UNC_P_PKG_RESIDENCY_C1E_CYCLES

Package C State Residency - C1E

UNC_P_PKG_RESIDENCY_C2E_CYCLES

Package C State Residency - C2E

UNC_P_PKG_RESIDENCY_C3_CYCLES

Package C State Residency - C3

UNC_P_PKG_RESIDENCY_C6_CYCLES

Package C State Residency - C6

UNC_P_PKG_RESIDENCY_C7_CYCLES

Package C7 State Residency

UNC_P_POWER_STATE_OCCUPANCY.CORES_C0

Number of cores in C-State; C0 and C1

UNC_P_POWER_STATE_OCCUPANCY.CORES_C3

Number of cores in C-State; C3

UNC_P_POWER_STATE_OCCUPANCY.CORES_C6

Number of cores in C-State; C6 and C7

UNC_P_PROCHOT_EXTERNAL_CYCLES

External Prochot

UNC_P_PROCHOT_INTERNAL_CYCLES

Internal Prochot

UNC_P_TOTAL_TRANSITION_CYCLES

Total Core C State Transition Cycles

UNC_P_UFS_TRANSITIONS_RING_GV

tbd

UNC_P_VR_HOT_CYCLES

VR Hot

UNC_Q_CLOCKTICKS

Number of qfclks

UNC_Q_CTO_COUNT

Count of CTO Events

UNC_Q_DIRECT2CORE.FAILURE_CREDITS

Direct 2 Core Spawning; Spawn Failure - Egress Credits

UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS

Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss

UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT

Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid

UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS

Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid

UNC_Q_DIRECT2CORE.FAILURE_MISS

Direct 2 Core Spawning; Spawn Failure - RBT Miss

UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT

Direct 2 Core Spawning; Spawn Failure - RBT Invalid

UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS

Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid

UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT

Direct 2 Core Spawning; Spawn Success

UNC_Q_L1_POWER_CYCLES

Cycles in L1

UNC_Q_RxL0P_POWER_CYCLES

Cycles in L0p

UNC_Q_RxL0_POWER_CYCLES

Cycles in L0

UNC_Q_RxL_BYPASSED

Rx Flit Buffer Bypassed

UNC_Q_RxL_CRC_ERRORS.NORMAL_OP

CRC Errors Detected; Normal Operations

UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS

VN0 Credit Consumed; DRS

UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM

VN0 Credit Consumed; HOM

UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB

VN0 Credit Consumed; NCB

UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS

VN0 Credit Consumed; NCS

UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR

VN0 Credit Consumed; NDR

UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP

VN0 Credit Consumed; SNP

UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS

VN1 Credit Consumed; DRS

UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM

VN1 Credit Consumed; HOM

UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB

VN1 Credit Consumed; NCB

UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS

VN1 Credit Consumed; NCS

UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR

VN1 Credit Consumed; NDR

UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP

VN1 Credit Consumed; SNP

UNC_Q_RxL_CREDITS_CONSUMED_VNA

VNA Credit Consumed

UNC_Q_RxL_CYCLES_NE

RxQ Cycles Not Empty

UNC_Q_RxL_CYCLES_NE_DRS.VN0

RxQ Cycles Not Empty - DRS; for VN0

UNC_Q_RxL_CYCLES_NE_DRS.VN1

RxQ Cycles Not Empty - DRS; for VN1

UNC_Q_RxL_CYCLES_NE_HOM.VN0

RxQ Cycles Not Empty - HOM; for VN0

UNC_Q_RxL_CYCLES_NE_HOM.VN1

RxQ Cycles Not Empty - HOM; for VN1

UNC_Q_RxL_CYCLES_NE_NCB.VN0

RxQ Cycles Not Empty - NCB; for VN0

UNC_Q_RxL_CYCLES_NE_NCB.VN1

RxQ Cycles Not Empty - NCB; for VN1

UNC_Q_RxL_CYCLES_NE_NCS.VN0

RxQ Cycles Not Empty - NCS; for VN0

UNC_Q_RxL_CYCLES_NE_NCS.VN1

RxQ Cycles Not Empty - NCS; for VN1

UNC_Q_RxL_CYCLES_NE_NDR.VN0

RxQ Cycles Not Empty - NDR; for VN0

UNC_Q_RxL_CYCLES_NE_NDR.VN1

RxQ Cycles Not Empty - NDR; for VN1

UNC_Q_RxL_CYCLES_NE_SNP.VN0

RxQ Cycles Not Empty - SNP; for VN0

UNC_Q_RxL_CYCLES_NE_SNP.VN1

RxQ Cycles Not Empty - SNP; for VN1

UNC_Q_RxL_FLITS_G0.IDLE

Flits Received - Group 0; Idle and Null Flits

UNC_Q_RxL_FLITS_G1.DRS

Flits Received - Group 1; DRS Flits (both Header and Data)

UNC_Q_RxL_FLITS_G1.DRS_DATA

Flits Received - Group 1; DRS Data Flits

UNC_Q_RxL_FLITS_G1.DRS_NONDATA

Flits Received - Group 1; DRS Header Flits

UNC_Q_RxL_FLITS_G1.HOM

Flits Received - Group 1; HOM Flits

UNC_Q_RxL_FLITS_G1.HOM_NONREQ

Flits Received - Group 1; HOM Non-Request Flits

UNC_Q_RxL_FLITS_G1.HOM_REQ

Flits Received - Group 1; HOM Request Flits

UNC_Q_RxL_FLITS_G1.SNP

Flits Received - Group 1; SNP Flits

UNC_Q_RxL_FLITS_G2.NCB

Flits Received - Group 2; Non-Coherent Rx Flits

UNC_Q_RxL_FLITS_G2.NCB_DATA

Flits Received - Group 2; Non-Coherent data Rx Flits

UNC_Q_RxL_FLITS_G2.NCB_NONDATA

Flits Received - Group 2; Non-Coherent non-data Rx Flits

UNC_Q_RxL_FLITS_G2.NCS

Flits Received - Group 2; Non-Coherent standard Rx Flits

UNC_Q_RxL_FLITS_G2.NDR_AD

Flits Received - Group 2; Non-Data Response Rx Flits - AD

UNC_Q_RxL_FLITS_G2.NDR_AK

Flits Received - Group 2; Non-Data Response Rx Flits - AK

UNC_Q_RxL_INSERTS

Rx Flit Buffer Allocations

UNC_Q_RxL_INSERTS_DRS.VN0

Rx Flit Buffer Allocations - DRS; for VN0

UNC_Q_RxL_INSERTS_DRS.VN1

Rx Flit Buffer Allocations - DRS; for VN1

UNC_Q_RxL_INSERTS_HOM.VN0

Rx Flit Buffer Allocations - HOM; for VN0

UNC_Q_RxL_INSERTS_HOM.VN1

Rx Flit Buffer Allocations - HOM; for VN1

UNC_Q_RxL_INSERTS_NCB.VN0

Rx Flit Buffer Allocations - NCB; for VN0

UNC_Q_RxL_INSERTS_NCB.VN1

Rx Flit Buffer Allocations - NCB; for VN1

UNC_Q_RxL_INSERTS_NCS.VN0

Rx Flit Buffer Allocations - NCS; for VN0

UNC_Q_RxL_INSERTS_NCS.VN1

Rx Flit Buffer Allocations - NCS; for VN1

UNC_Q_RxL_INSERTS_NDR.VN0

Rx Flit Buffer Allocations - NDR; for VN0

UNC_Q_RxL_INSERTS_NDR.VN1

Rx Flit Buffer Allocations - NDR; for VN1

UNC_Q_RxL_INSERTS_SNP.VN0

Rx Flit Buffer Allocations - SNP; for VN0

UNC_Q_RxL_INSERTS_SNP.VN1

Rx Flit Buffer Allocations - SNP; for VN1

UNC_Q_RxL_OCCUPANCY

RxQ Occupancy - All Packets

UNC_Q_RxL_OCCUPANCY_DRS.VN0

RxQ Occupancy - DRS; for VN0

UNC_Q_RxL_OCCUPANCY_DRS.VN1

RxQ Occupancy - DRS; for VN1

UNC_Q_RxL_OCCUPANCY_HOM.VN0

RxQ Occupancy - HOM; for VN0

UNC_Q_RxL_OCCUPANCY_HOM.VN1

RxQ Occupancy - HOM; for VN1

UNC_Q_RxL_OCCUPANCY_NCB.VN0

RxQ Occupancy - NCB; for VN0

UNC_Q_RxL_OCCUPANCY_NCB.VN1

RxQ Occupancy - NCB; for VN1

UNC_Q_RxL_OCCUPANCY_NCS.VN0

RxQ Occupancy - NCS; for VN0

UNC_Q_RxL_OCCUPANCY_NCS.VN1

RxQ Occupancy - NCS; for VN1

UNC_Q_RxL_OCCUPANCY_NDR.VN0

RxQ Occupancy - NDR; for VN0

UNC_Q_RxL_OCCUPANCY_NDR.VN1

RxQ Occupancy - NDR; for VN1

UNC_Q_RxL_OCCUPANCY_SNP.VN0

RxQ Occupancy - SNP; for VN0

UNC_Q_RxL_OCCUPANCY_SNP.VN1

RxQ Occupancy - SNP; for VN1

UNC_Q_RxL_STALLS_VN0.BGF_DRS

Stalls Sending to R3QPI on VN0; BGF Stall - HOM

UNC_Q_RxL_STALLS_VN0.BGF_HOM

Stalls Sending to R3QPI on VN0; BGF Stall - DRS

UNC_Q_RxL_STALLS_VN0.BGF_NCB

Stalls Sending to R3QPI on VN0; BGF Stall - SNP

UNC_Q_RxL_STALLS_VN0.BGF_NCS

Stalls Sending to R3QPI on VN0; BGF Stall - NDR

UNC_Q_RxL_STALLS_VN0.BGF_NDR

Stalls Sending to R3QPI on VN0; BGF Stall - NCS

UNC_Q_RxL_STALLS_VN0.BGF_SNP

Stalls Sending to R3QPI on VN0; BGF Stall - NCB

UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS

Stalls Sending to R3QPI on VN0; Egress Credits

UNC_Q_RxL_STALLS_VN0.GV

Stalls Sending to R3QPI on VN0; GV

UNC_Q_RxL_STALLS_VN1.BGF_DRS

Stalls Sending to R3QPI on VN1; BGF Stall - HOM

UNC_Q_RxL_STALLS_VN1.BGF_HOM

Stalls Sending to R3QPI on VN1; BGF Stall - DRS

UNC_Q_RxL_STALLS_VN1.BGF_NCB

Stalls Sending to R3QPI on VN1; BGF Stall - SNP

UNC_Q_RxL_STALLS_VN1.BGF_NCS

Stalls Sending to R3QPI on VN1; BGF Stall - NDR

UNC_Q_RxL_STALLS_VN1.BGF_NDR

Stalls Sending to R3QPI on VN1; BGF Stall - NCS

UNC_Q_RxL_STALLS_VN1.BGF_SNP

Stalls Sending to R3QPI on VN1; BGF Stall - NCB

UNC_Q_TxL0P_POWER_CYCLES

Cycles in L0p

UNC_Q_TxL0_POWER_CYCLES

Cycles in L0

UNC_Q_TxL_BYPASSED

Tx Flit Buffer Bypassed

UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL

Cycles Stalled with no LLR Credits; LLR is almost full

UNC_Q_TxL_CRC_NO_CREDITS.FULL

Cycles Stalled with no LLR Credits; LLR is full

UNC_Q_TxL_CYCLES_NE

Tx Flit Buffer Cycles not Empty

UNC_Q_TxL_FLITS_G0.DATA

Flits Transferred - Group 0; Data Tx Flits

UNC_Q_TxL_FLITS_G0.NON_DATA

Flits Transferred - Group 0; Non-Data protocol Tx Flits

UNC_Q_TxL_FLITS_G1.DRS

Flits Transferred - Group 1; DRS Flits (both Header and Data)

UNC_Q_TxL_FLITS_G1.DRS_DATA

Flits Transferred - Group 1; DRS Data Flits

UNC_Q_TxL_FLITS_G1.DRS_NONDATA

Flits Transferred - Group 1; DRS Header Flits

UNC_Q_TxL_FLITS_G1.HOM

Flits Transferred - Group 1; HOM Flits

UNC_Q_TxL_FLITS_G1.HOM_NONREQ

Flits Transferred - Group 1; HOM Non-Request Flits

UNC_Q_TxL_FLITS_G1.HOM_REQ

Flits Transferred - Group 1; HOM Request Flits

UNC_Q_TxL_FLITS_G1.SNP

Flits Transferred - Group 1; SNP Flits

UNC_Q_TxL_FLITS_G2.NCB

Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits

UNC_Q_TxL_FLITS_G2.NCB_DATA

Flits Transferred - Group 2; Non-Coherent data Tx Flits

UNC_Q_TxL_FLITS_G2.NCB_NONDATA

Flits Transferred - Group 2; Non-Coherent non-data Tx Flits

UNC_Q_TxL_FLITS_G2.NCS

Flits Transferred - Group 2; Non-Coherent standard Tx Flits

UNC_Q_TxL_FLITS_G2.NDR_AD

Flits Transferred - Group 2; Non-Data Response Tx Flits - AD

UNC_Q_TxL_FLITS_G2.NDR_AK

Flits Transferred - Group 2; Non-Data Response Tx Flits - AK

UNC_Q_TxL_INSERTS

Tx Flit Buffer Allocations

UNC_Q_TxL_OCCUPANCY

Tx Flit Buffer Occupancy

UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0

R3QPI Egress Credit Occupancy - HOM; for VN0

UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1

R3QPI Egress Credit Occupancy - HOM; for VN1

UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0

R3QPI Egress Credit Occupancy - AD HOM; for VN0

UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1

R3QPI Egress Credit Occupancy - AD HOM; for VN1

UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0

R3QPI Egress Credit Occupancy - AD NDR; for VN0

UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1

R3QPI Egress Credit Occupancy - AD NDR; for VN1

UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0

R3QPI Egress Credit Occupancy - AD NDR; for VN0

UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1

R3QPI Egress Credit Occupancy - AD NDR; for VN1

UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0

R3QPI Egress Credit Occupancy - SNP; for VN0

UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1

R3QPI Egress Credit Occupancy - SNP; for VN1

UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0

R3QPI Egress Credit Occupancy - AD SNP; for VN0

UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1

R3QPI Egress Credit Occupancy - AD SNP; for VN1

UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED

R3QPI Egress Credit Occupancy - AK NDR

UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY

R3QPI Egress Credit Occupancy - AK NDR

UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0

R3QPI Egress Credit Occupancy - DRS; for VN0

UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1

R3QPI Egress Credit Occupancy - DRS; for VN1

UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR

R3QPI Egress Credit Occupancy - DRS; for Shared VN

UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0

R3QPI Egress Credit Occupancy - BL DRS; for VN0

UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1

R3QPI Egress Credit Occupancy - BL DRS; for VN1

UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR

R3QPI Egress Credit Occupancy - BL DRS; for Shared VN

UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0

R3QPI Egress Credit Occupancy - NCB; for VN0

UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1

R3QPI Egress Credit Occupancy - NCB; for VN1

UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0

R3QPI Egress Credit Occupancy - BL NCB; for VN0

UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1

R3QPI Egress Credit Occupancy - BL NCB; for VN1

UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0

R3QPI Egress Credit Occupancy - NCS; for VN0

UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1

R3QPI Egress Credit Occupancy - NCS; for VN1

UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0

R3QPI Egress Credit Occupancy - BL NCS; for VN0

UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1

R3QPI Egress Credit Occupancy - BL NCS; for VN1

UNC_Q_VNA_CREDIT_RETURNS

VNA Credits Returned

UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY

VNA Credits Pending Return - Occupancy

UNC_R2_CLOCKTICKS

Number of uclks in domain

UNC_R2_IIO_CREDIT.ISOCH_QPI0

tbd

UNC_R2_IIO_CREDIT.ISOCH_QPI1

tbd

UNC_R2_IIO_CREDIT.PRQ_QPI0

tbd

UNC_R2_IIO_CREDIT.PRQ_QPI1

tbd

UNC_R2_IIO_CREDITS_ACQUIRED.DRS

R2PCIe IIO Credit Acquired; DRS

UNC_R2_IIO_CREDITS_ACQUIRED.NCB

R2PCIe IIO Credit Acquired; NCB

UNC_R2_IIO_CREDITS_ACQUIRED.NCS

R2PCIe IIO Credit Acquired; NCS

UNC_R2_IIO_CREDITS_USED.DRS

R2PCIe IIO Credits in Use; DRS

UNC_R2_IIO_CREDITS_USED.NCB

R2PCIe IIO Credits in Use; NCB

UNC_R2_IIO_CREDITS_USED.NCS

R2PCIe IIO Credits in Use; NCS

UNC_R2_RING_AD_USED.ALL

R2 AD Ring in Use; All

UNC_R2_RING_AD_USED.CCW

R2 AD Ring in Use; Counterclockwise

UNC_R2_RING_AD_USED.CCW_EVEN

R2 AD Ring in Use; Counterclockwise and Even

UNC_R2_RING_AD_USED.CCW_ODD

R2 AD Ring in Use; Counterclockwise and Odd

UNC_R2_RING_AD_USED.CW

R2 AD Ring in Use; Clockwise

UNC_R2_RING_AD_USED.CW_EVEN

R2 AD Ring in Use; Clockwise and Even

UNC_R2_RING_AD_USED.CW_ODD

R2 AD Ring in Use; Clockwise and Odd

UNC_R2_RING_AK_BOUNCES.DN

AK Ingress Bounced; Dn

UNC_R2_RING_AK_BOUNCES.UP

AK Ingress Bounced; Up

UNC_R2_RING_AK_USED.ALL

R2 AK Ring in Use; All

UNC_R2_RING_AK_USED.CCW

R2 AK Ring in Use; Counterclockwise

UNC_R2_RING_AK_USED.CCW_EVEN

R2 AK Ring in Use; Counterclockwise and Even

UNC_R2_RING_AK_USED.CCW_ODD

R2 AK Ring in Use; Counterclockwise and Odd

UNC_R2_RING_AK_USED.CW

R2 AK Ring in Use; Clockwise

UNC_R2_RING_AK_USED.CW_EVEN

R2 AK Ring in Use; Clockwise and Even

UNC_R2_RING_AK_USED.CW_ODD

R2 AK Ring in Use; Clockwise and Odd

UNC_R2_RING_BL_USED.ALL

R2 BL Ring in Use; All

UNC_R2_RING_BL_USED.CCW

R2 BL Ring in Use; Counterclockwise

UNC_R2_RING_BL_USED.CCW_EVEN

R2 BL Ring in Use; Counterclockwise and Even

UNC_R2_RING_BL_USED.CCW_ODD

R2 BL Ring in Use; Counterclockwise and Odd

UNC_R2_RING_BL_USED.CW

R2 BL Ring in Use; Clockwise

UNC_R2_RING_BL_USED.CW_EVEN

R2 BL Ring in Use; Clockwise and Even

UNC_R2_RING_BL_USED.CW_ODD

R2 BL Ring in Use; Clockwise and Odd

UNC_R2_RING_IV_USED.ANY

R2 IV Ring in Use; Any

UNC_R2_RING_IV_USED.CCW

R2 IV Ring in Use; Counterclockwise

UNC_R2_RING_IV_USED.CW

R2 IV Ring in Use; Clockwise

UNC_R2_RxR_CYCLES_NE.NCB

Ingress Cycles Not Empty; NCB

UNC_R2_RxR_CYCLES_NE.NCS

Ingress Cycles Not Empty; NCS

UNC_R2_RxR_INSERTS.NCB

Ingress Allocations; NCB

UNC_R2_RxR_INSERTS.NCS

Ingress Allocations; NCS

UNC_R2_RxR_OCCUPANCY.DRS

Ingress Occupancy Accumulator; DRS

UNC_R2_SBO0_CREDITS_ACQUIRED.AD

SBo0 Credits Acquired; For AD Ring

UNC_R2_SBO0_CREDITS_ACQUIRED.BL

SBo0 Credits Acquired; For BL Ring

UNC_R2_SBO0_CREDIT_OCCUPANCY.AD

SBo0 Credits Occupancy; For AD Ring

UNC_R2_SBO0_CREDIT_OCCUPANCY.BL

SBo0 Credits Occupancy; For BL Ring

UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD

Stall on No Sbo Credits; For SBo0, AD Ring

UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL

Stall on No Sbo Credits; For SBo0, BL Ring

UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD

Stall on No Sbo Credits; For SBo1, AD Ring

UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL

Stall on No Sbo Credits; For SBo1, BL Ring

UNC_R2_TxR_CYCLES_FULL.AD

Egress Cycles Full; AD

UNC_R2_TxR_CYCLES_FULL.AK

Egress Cycles Full; AK

UNC_R2_TxR_CYCLES_FULL.BL

Egress Cycles Full; BL

UNC_R2_TxR_CYCLES_NE.AD

Egress Cycles Not Empty; AD

UNC_R2_TxR_CYCLES_NE.AK

Egress Cycles Not Empty; AK

UNC_R2_TxR_CYCLES_NE.BL

Egress Cycles Not Empty; BL

UNC_R2_TxR_NACK_CW.DN_AD

Egress CCW NACK; AD CCW

UNC_R2_TxR_NACK_CW.DN_AK

Egress CCW NACK; AK CCW

UNC_R2_TxR_NACK_CW.DN_BL

Egress CCW NACK; BL CCW

UNC_R2_TxR_NACK_CW.UP_AD

Egress CCW NACK; AK CCW

UNC_R2_TxR_NACK_CW.UP_AK

Egress CCW NACK; BL CW

UNC_R2_TxR_NACK_CW.UP_BL

Egress CCW NACK; BL CCW

UNC_R3_CLOCKTICKS

Number of uclks in domain

UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10

CBox AD Credits Empty

UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11

CBox AD Credits Empty

UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12

CBox AD Credits Empty

UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13

CBox AD Credits Empty

UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16

CBox AD Credits Empty

UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8

CBox AD Credits Empty

UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9

CBox AD Credits Empty

UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17

CBox AD Credits Empty

UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0

CBox AD Credits Empty

UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1

CBox AD Credits Empty

UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2

CBox AD Credits Empty

UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3

CBox AD Credits Empty

UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4

CBox AD Credits Empty

UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5

CBox AD Credits Empty

UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6

CBox AD Credits Empty

UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7

CBox AD Credits Empty

UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0

HA/R2 AD Credits Empty

UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1

HA/R2 AD Credits Empty

UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB

HA/R2 AD Credits Empty

UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS

HA/R2 AD Credits Empty

UNC_R3_IOT_BACKPRESSURE.HUB

IOT Backpressure

UNC_R3_IOT_BACKPRESSURE.SAT

IOT Backpressure

UNC_R3_IOT_CTS_HI.CTS2

IOT Common Trigger Sequencer - Hi

UNC_R3_IOT_CTS_HI.CTS3

IOT Common Trigger Sequencer - Hi

UNC_R3_IOT_CTS_LO.CTS0

IOT Common Trigger Sequencer - Lo

UNC_R3_IOT_CTS_LO.CTS1

IOT Common Trigger Sequencer - Lo

UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM

QPI0 AD Credits Empty

UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR

QPI0 AD Credits Empty

UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP

QPI0 AD Credits Empty

UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM

QPI0 AD Credits Empty

UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR

QPI0 AD Credits Empty

UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP

QPI0 AD Credits Empty

UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA

QPI0 AD Credits Empty

UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM

QPI0 BL Credits Empty

UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR

QPI0 BL Credits Empty

UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP

QPI0 BL Credits Empty

UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA

QPI0 BL Credits Empty

UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM

QPI1 AD Credits Empty

UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR

QPI1 AD Credits Empty

UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP

QPI1 AD Credits Empty

UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA

QPI1 AD Credits Empty

UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM

QPI1 BL Credits Empty

UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR

QPI1 BL Credits Empty

UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP

QPI1 BL Credits Empty

UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM

QPI1 BL Credits Empty

UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR

QPI1 BL Credits Empty

UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP

QPI1 BL Credits Empty

UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA

QPI1 BL Credits Empty

UNC_R3_RING_AD_USED.ALL

R3 AD Ring in Use; All

UNC_R3_RING_AD_USED.CCW

R3 AD Ring in Use; Counterclockwise

UNC_R3_RING_AD_USED.CCW_EVEN

R3 AD Ring in Use; Counterclockwise and Even

UNC_R3_RING_AD_USED.CCW_ODD

R3 AD Ring in Use; Counterclockwise and Odd

UNC_R3_RING_AD_USED.CW

R3 AD Ring in Use; Clockwise

UNC_R3_RING_AD_USED.CW_EVEN

R3 AD Ring in Use; Clockwise and Even

UNC_R3_RING_AD_USED.CW_ODD

R3 AD Ring in Use; Clockwise and Odd

UNC_R3_RING_AK_USED.ALL

R3 AK Ring in Use; All

UNC_R3_RING_AK_USED.CCW

R3 AK Ring in Use; Counterclockwise

UNC_R3_RING_AK_USED.CCW_EVEN

R3 AK Ring in Use; Counterclockwise and Even

UNC_R3_RING_AK_USED.CCW_ODD

R3 AK Ring in Use; Counterclockwise and Odd

UNC_R3_RING_AK_USED.CW

R3 AK Ring in Use; Clockwise

UNC_R3_RING_AK_USED.CW_EVEN

R3 AK Ring in Use; Clockwise and Even

UNC_R3_RING_AK_USED.CW_ODD

R3 AK Ring in Use; Clockwise and Odd

UNC_R3_RING_BL_USED.ALL

R3 BL Ring in Use; All

UNC_R3_RING_BL_USED.CCW

R3 BL Ring in Use; Counterclockwise

UNC_R3_RING_BL_USED.CCW_EVEN

R3 BL Ring in Use; Counterclockwise and Even

UNC_R3_RING_BL_USED.CCW_ODD

R3 BL Ring in Use; Counterclockwise and Odd

UNC_R3_RING_BL_USED.CW

R3 BL Ring in Use; Clockwise

UNC_R3_RING_BL_USED.CW_EVEN

R3 BL Ring in Use; Clockwise and Even

UNC_R3_RING_BL_USED.CW_ODD

R3 BL Ring in Use; Clockwise and Odd

UNC_R3_RING_IV_USED.ANY

R3 IV Ring in Use; Any

UNC_R3_RING_IV_USED.CW

R3 IV Ring in Use; Clockwise

UNC_R3_RING_SINK_STARVED.AK

Ring Stop Starved; AK

UNC_R3_RxR_CYCLES_NE.HOM

Ingress Cycles Not Empty; HOM

UNC_R3_RxR_CYCLES_NE.NDR

Ingress Cycles Not Empty; NDR

UNC_R3_RxR_CYCLES_NE.SNP

Ingress Cycles Not Empty; SNP

UNC_R3_RxR_CYCLES_NE_VN1.DRS

VN1 Ingress Cycles Not Empty; DRS

UNC_R3_RxR_CYCLES_NE_VN1.HOM

VN1 Ingress Cycles Not Empty; HOM

UNC_R3_RxR_CYCLES_NE_VN1.NCB

VN1 Ingress Cycles Not Empty; NCB

UNC_R3_RxR_CYCLES_NE_VN1.NCS

VN1 Ingress Cycles Not Empty; NCS

UNC_R3_RxR_CYCLES_NE_VN1.NDR

VN1 Ingress Cycles Not Empty; NDR

UNC_R3_RxR_CYCLES_NE_VN1.SNP

VN1 Ingress Cycles Not Empty; SNP

UNC_R3_RxR_INSERTS.DRS

Ingress Allocations; DRS

UNC_R3_RxR_INSERTS.HOM

Ingress Allocations; HOM

UNC_R3_RxR_INSERTS.NCB

Ingress Allocations; NCB

UNC_R3_RxR_INSERTS.NCS

Ingress Allocations; NCS

UNC_R3_RxR_INSERTS.NDR

Ingress Allocations; NDR

UNC_R3_RxR_INSERTS.SNP

Ingress Allocations; SNP

UNC_R3_RxR_INSERTS_VN1.DRS

VN1 Ingress Allocations; DRS

UNC_R3_RxR_INSERTS_VN1.HOM

VN1 Ingress Allocations; HOM

UNC_R3_RxR_INSERTS_VN1.NCB

VN1 Ingress Allocations; NCB

UNC_R3_RxR_INSERTS_VN1.NCS

VN1 Ingress Allocations; NCS

UNC_R3_RxR_INSERTS_VN1.NDR

VN1 Ingress Allocations; NDR

UNC_R3_RxR_INSERTS_VN1.SNP

VN1 Ingress Allocations; SNP

UNC_R3_RxR_OCCUPANCY_VN1.DRS

VN1 Ingress Occupancy Accumulator; DRS

UNC_R3_RxR_OCCUPANCY_VN1.HOM

VN1 Ingress Occupancy Accumulator; HOM

UNC_R3_RxR_OCCUPANCY_VN1.NCB

VN1 Ingress Occupancy Accumulator; NCB

UNC_R3_RxR_OCCUPANCY_VN1.NCS

VN1 Ingress Occupancy Accumulator; NCS

UNC_R3_RxR_OCCUPANCY_VN1.NDR

VN1 Ingress Occupancy Accumulator; NDR

UNC_R3_RxR_OCCUPANCY_VN1.SNP

VN1 Ingress Occupancy Accumulator; SNP

UNC_R3_SBO0_CREDITS_ACQUIRED.AD

SBo0 Credits Acquired; For AD Ring

UNC_R3_SBO0_CREDITS_ACQUIRED.BL

SBo0 Credits Acquired; For BL Ring

UNC_R3_SBO0_CREDIT_OCCUPANCY.AD

SBo0 Credits Occupancy; For AD Ring

UNC_R3_SBO0_CREDIT_OCCUPANCY.BL

SBo0 Credits Occupancy; For BL Ring

UNC_R3_SBO1_CREDITS_ACQUIRED.AD

SBo1 Credits Acquired; For AD Ring

UNC_R3_SBO1_CREDITS_ACQUIRED.BL

SBo1 Credits Acquired; For BL Ring

UNC_R3_SBO1_CREDIT_OCCUPANCY.AD

SBo1 Credits Occupancy; For AD Ring

UNC_R3_SBO1_CREDIT_OCCUPANCY.BL

SBo1 Credits Occupancy; For BL Ring

UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD

Stall on No Sbo Credits; For SBo0, AD Ring

UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL

Stall on No Sbo Credits; For SBo0, BL Ring

UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD

Stall on No Sbo Credits; For SBo1, AD Ring

UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL

Stall on No Sbo Credits; For SBo1, BL Ring

UNC_R3_TxR_NACK.DN_AD

Egress CCW NACK; AD CCW

UNC_R3_TxR_NACK.DN_AK

Egress CCW NACK; AK CCW

UNC_R3_TxR_NACK.DN_BL

Egress CCW NACK; BL CCW

UNC_R3_TxR_NACK.UP_AD

Egress CCW NACK; AK CCW

UNC_R3_TxR_NACK.UP_AK

Egress CCW NACK; BL CW

UNC_R3_TxR_NACK.UP_BL

Egress CCW NACK; BL CCW

UNC_R3_VN0_CREDITS_REJECT.DRS

VN0 Credit Acquisition Failed on DRS; DRS Message Class

UNC_R3_VN0_CREDITS_REJECT.HOM

VN0 Credit Acquisition Failed on DRS; HOM Message Class

UNC_R3_VN0_CREDITS_REJECT.NCB

VN0 Credit Acquisition Failed on DRS; NCB Message Class

UNC_R3_VN0_CREDITS_REJECT.NCS

VN0 Credit Acquisition Failed on DRS; NCS Message Class

UNC_R3_VN0_CREDITS_REJECT.NDR

VN0 Credit Acquisition Failed on DRS; NDR Message Class

UNC_R3_VN0_CREDITS_REJECT.SNP

VN0 Credit Acquisition Failed on DRS; SNP Message Class

UNC_R3_VN0_CREDITS_USED.DRS

VN0 Credit Used; DRS Message Class

UNC_R3_VN0_CREDITS_USED.HOM

VN0 Credit Used; HOM Message Class

UNC_R3_VN0_CREDITS_USED.NCB

VN0 Credit Used; NCB Message Class

UNC_R3_VN0_CREDITS_USED.NCS

VN0 Credit Used; NCS Message Class

UNC_R3_VN0_CREDITS_USED.NDR

VN0 Credit Used; NDR Message Class

UNC_R3_VN0_CREDITS_USED.SNP

VN0 Credit Used; SNP Message Class

UNC_R3_VN1_CREDITS_REJECT.DRS

VN1 Credit Acquisition Failed on DRS; DRS Message Class

UNC_R3_VN1_CREDITS_REJECT.HOM

VN1 Credit Acquisition Failed on DRS; HOM Message Class

UNC_R3_VN1_CREDITS_REJECT.NCB

VN1 Credit Acquisition Failed on DRS; NCB Message Class

UNC_R3_VN1_CREDITS_REJECT.NCS

VN1 Credit Acquisition Failed on DRS; NCS Message Class

UNC_R3_VN1_CREDITS_REJECT.NDR

VN1 Credit Acquisition Failed on DRS; NDR Message Class

UNC_R3_VN1_CREDITS_REJECT.SNP

VN1 Credit Acquisition Failed on DRS; SNP Message Class

UNC_R3_VN1_CREDITS_USED.DRS

VN1 Credit Used; DRS Message Class

UNC_R3_VN1_CREDITS_USED.HOM

VN1 Credit Used; HOM Message Class

UNC_R3_VN1_CREDITS_USED.NCB

VN1 Credit Used; NCB Message Class

UNC_R3_VN1_CREDITS_USED.NCS

VN1 Credit Used; NCS Message Class

UNC_R3_VN1_CREDITS_USED.NDR

VN1 Credit Used; NDR Message Class

UNC_R3_VN1_CREDITS_USED.SNP

VN1 Credit Used; SNP Message Class

UNC_R3_VNA_CREDITS_ACQUIRED.AD

VNA credit Acquisitions; HOM Message Class

UNC_R3_VNA_CREDITS_ACQUIRED.BL

VNA credit Acquisitions; HOM Message Class

UNC_R3_VNA_CREDITS_REJECT.DRS

VNA Credit Reject; DRS Message Class

UNC_R3_VNA_CREDITS_REJECT.HOM

VNA Credit Reject; HOM Message Class

UNC_R3_VNA_CREDITS_REJECT.NCB

VNA Credit Reject; NCB Message Class

UNC_R3_VNA_CREDITS_REJECT.NCS

VNA Credit Reject; NCS Message Class

UNC_R3_VNA_CREDITS_REJECT.NDR

VNA Credit Reject; NDR Message Class

UNC_R3_VNA_CREDITS_REJECT.SNP

VNA Credit Reject; SNP Message Class

UNC_S_BOUNCE_CONTROL

Bounce Control

UNC_S_CLOCKTICKS

Uncore Clocks

UNC_S_FAST_ASSERTED

FaST wire asserted

UNC_S_RING_AD_USED.ALL

AD Ring In Use; All

UNC_S_RING_AD_USED.DOWN

AD Ring In Use; Down

UNC_S_RING_AD_USED.DOWN_EVEN

AD Ring In Use; Down and Event

UNC_S_RING_AD_USED.DOWN_ODD

AD Ring In Use; Down and Odd

UNC_S_RING_AD_USED.UP

AD Ring In Use; Up

UNC_S_RING_AD_USED.UP_EVEN

AD Ring In Use; Up and Even

UNC_S_RING_AD_USED.UP_ODD

AD Ring In Use; Up and Odd

UNC_S_RING_AK_USED.ALL

AK Ring In Use; All

UNC_S_RING_AK_USED.DOWN

AK Ring In Use; Down

UNC_S_RING_AK_USED.DOWN_EVEN

AK Ring In Use; Down and Event

UNC_S_RING_AK_USED.DOWN_ODD

AK Ring In Use; Down and Odd

UNC_S_RING_AK_USED.UP

AK Ring In Use; Up

UNC_S_RING_AK_USED.UP_EVEN

AK Ring In Use; Up and Even

UNC_S_RING_AK_USED.UP_ODD

AK Ring In Use; Up and Odd

UNC_S_RING_BL_USED.ALL

BL Ring in Use; All

UNC_S_RING_BL_USED.DOWN

BL Ring in Use; Down

UNC_S_RING_BL_USED.DOWN_EVEN

BL Ring in Use; Down and Event

UNC_S_RING_BL_USED.DOWN_ODD

BL Ring in Use; Down and Odd

UNC_S_RING_BL_USED.UP

BL Ring in Use; Up

UNC_S_RING_BL_USED.UP_EVEN

BL Ring in Use; Up and Even

UNC_S_RING_BL_USED.UP_ODD

BL Ring in Use; Up and Odd

UNC_S_RING_BOUNCES.AD_CACHE

Number of LLC responses that bounced on the Ring.

UNC_S_RING_BOUNCES.AK_CORE

Number of LLC responses that bounced on the Ring.; Acknowledgements to core

UNC_S_RING_BOUNCES.BL_CORE

Number of LLC responses that bounced on the Ring.; Data Responses to core

UNC_S_RING_BOUNCES.IV_CORE

Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.

UNC_S_RING_IV_USED.DN

BL Ring in Use; Any

UNC_S_RING_IV_USED.UP

BL Ring in Use; Any

UNC_S_RING_SINK_STARVED.AD_CACHE

tbd

UNC_S_RING_SINK_STARVED.AK_CORE

tbd

UNC_S_RING_SINK_STARVED.BL_CORE

tbd

UNC_S_RING_SINK_STARVED.IV_CORE

tbd

UNC_S_RxR_BUSY_STARVED.AD_BNC

Injection Starvation; AD - Bounces

UNC_S_RxR_BUSY_STARVED.AD_CRD

Injection Starvation; AD - Credits

UNC_S_RxR_BUSY_STARVED.BL_BNC

Injection Starvation; BL - Bounces

UNC_S_RxR_BUSY_STARVED.BL_CRD

Injection Starvation; BL - Credits

UNC_S_RxR_BYPASS.AD_BNC

Bypass; AD - Bounces

UNC_S_RxR_BYPASS.AD_CRD

Bypass; AD - Credits

UNC_S_RxR_BYPASS.AK

Bypass; AK

UNC_S_RxR_BYPASS.BL_BNC

Bypass; BL - Bounces

UNC_S_RxR_BYPASS.BL_CRD

Bypass; BL - Credits

UNC_S_RxR_BYPASS.IV

Bypass; IV

UNC_S_RxR_CRD_STARVED.AD_BNC

Injection Starvation; AD - Bounces

UNC_S_RxR_CRD_STARVED.AD_CRD

Injection Starvation; AD - Credits

UNC_S_RxR_CRD_STARVED.AK

Injection Starvation; AK

UNC_S_RxR_CRD_STARVED.BL_BNC

Injection Starvation; BL - Bounces

UNC_S_RxR_CRD_STARVED.BL_CRD

Injection Starvation; BL - Credits

UNC_S_RxR_CRD_STARVED.IFV

Injection Starvation; IVF Credit

UNC_S_RxR_CRD_STARVED.IV

Injection Starvation; IV

UNC_S_RxR_INSERTS.AD_BNC

Ingress Allocations; AD - Bounces

UNC_S_RxR_INSERTS.AD_CRD

Ingress Allocations; AD - Credits

UNC_S_RxR_INSERTS.AK

Ingress Allocations; AK

UNC_S_RxR_INSERTS.BL_BNC

Ingress Allocations; BL - Bounces

UNC_S_RxR_INSERTS.BL_CRD

Ingress Allocations; BL - Credits

UNC_S_RxR_INSERTS.IV

Ingress Allocations; IV

UNC_S_RxR_OCCUPANCY.AD_BNC

Ingress Occupancy; AD - Bounces

UNC_S_RxR_OCCUPANCY.AD_CRD

Ingress Occupancy; AD - Credits

UNC_S_RxR_OCCUPANCY.AK

Ingress Occupancy; AK

UNC_S_RxR_OCCUPANCY.BL_BNC

Ingress Occupancy; BL - Bounces

UNC_S_RxR_OCCUPANCY.BL_CRD

Ingress Occupancy; BL - Credits

UNC_S_RxR_OCCUPANCY.IV

Ingress Occupancy; IV

UNC_S_TxR_ADS_USED.AD

tbd

UNC_S_TxR_ADS_USED.AK

tbd

UNC_S_TxR_ADS_USED.BL

tbd

UNC_S_TxR_INSERTS.AD_BNC

Egress Allocations; AD - Bounces

UNC_S_TxR_INSERTS.AD_CRD

Egress Allocations; AD - Credits

UNC_S_TxR_INSERTS.AK

Egress Allocations; AK

UNC_S_TxR_INSERTS.BL_BNC

Egress Allocations; BL - Bounces

UNC_S_TxR_INSERTS.BL_CRD

Egress Allocations; BL - Credits

UNC_S_TxR_INSERTS.IV

Egress Allocations; IV

UNC_S_TxR_OCCUPANCY.AD_BNC

Egress Occupancy; AD - Bounces

UNC_S_TxR_OCCUPANCY.AD_CRD

Egress Occupancy; AD - Credits

UNC_S_TxR_OCCUPANCY.AK

Egress Occupancy; AK

UNC_S_TxR_OCCUPANCY.BL_BNC

Egress Occupancy; BL - Bounces

UNC_S_TxR_OCCUPANCY.BL_CRD

Egress Occupancy; BL - Credits

UNC_S_TxR_OCCUPANCY.IV

Egress Occupancy; IV

UNC_S_TxR_STARVED.AD

Injection Starvation; Onto AD Ring

UNC_S_TxR_STARVED.AK

Injection Starvation; Onto AK Ring

UNC_S_TxR_STARVED.BL

Injection Starvation; Onto BL Ring

UNC_S_TxR_STARVED.IV

Injection Starvation; Onto IV Ring

UNC_U_EVENT_MSG.DOORBELL_RCVD

VLW Received

UNC_U_FILTER_MATCH.DISABLE

Filter Match

UNC_U_FILTER_MATCH.ENABLE

Filter Match

UNC_U_FILTER_MATCH.U2C_DISABLE

Filter Match

UNC_U_FILTER_MATCH.U2C_ENABLE

Filter Match

UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK

Cycles PHOLD Assert to Ack; Assert to ACK

UNC_U_RACU_REQUESTS

RACU Request

UNC_U_U2C_EVENTS.CMC

Monitor Sent to T0; Correctable Machine Check

UNC_U_U2C_EVENTS.LIVELOCK

Monitor Sent to T0; Livelock

UNC_U_U2C_EVENTS.LTERROR

Monitor Sent to T0; LTError

UNC_U_U2C_EVENTS.MONITOR_T0

Monitor Sent to T0; Monitor T0

UNC_U_U2C_EVENTS.MONITOR_T1

Monitor Sent to T0; Monitor T1

UNC_U_U2C_EVENTS.OTHER

Monitor Sent to T0; Other

UNC_U_U2C_EVENTS.TRAP

Monitor Sent to T0; Trap

UNC_U_U2C_EVENTS.UMC

Monitor Sent to T0; Uncorrectable Machine Check

UOPS_DISPATCHED_PORT.PORT_0

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.

UOPS_DISPATCHED_PORT.PORT_1

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.

UOPS_DISPATCHED_PORT.PORT_2

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.

UOPS_DISPATCHED_PORT.PORT_3

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.

UOPS_DISPATCHED_PORT.PORT_4

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.

UOPS_DISPATCHED_PORT.PORT_5

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.

UOPS_DISPATCHED_PORT.PORT_6

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.

UOPS_DISPATCHED_PORT.PORT_7

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.

UOPS_EXECUTED.CORE

Number of uops executed from any thread

UOPS_EXECUTED.CORE_CYCLES_GE_1

Cycles at least 1 micro-op is executed from any thread on physical core

UOPS_EXECUTED.CORE_CYCLES_GE_2

Cycles at least 2 micro-op is executed from any thread on physical core

UOPS_EXECUTED.CORE_CYCLES_GE_3

Cycles at least 3 micro-op is executed from any thread on physical core

UOPS_EXECUTED.CORE_CYCLES_GE_4

Cycles at least 4 micro-op is executed from any thread on physical core

UOPS_EXECUTED.CORE_CYCLES_NONE

Cycles with no micro-ops executed from any thread on physical core

UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC

Cycles where at least 1 uop was executed per-thread

UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC

Cycles where at least 2 uops were executed per-thread

UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC

Cycles where at least 3 uops were executed per-thread

UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC

Cycles where at least 4 uops were executed per-thread

UOPS_EXECUTED.STALL_CYCLES

This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.

UOPS_EXECUTED.THREAD

Number of uops to be executed per-thread each cycle.

UOPS_EXECUTED_PORT.PORT_0

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.

UOPS_EXECUTED_PORT.PORT_0_CORE

Cycles per core when uops are exectuted in port 0

UOPS_EXECUTED_PORT.PORT_1

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.

UOPS_EXECUTED_PORT.PORT_1_CORE

Cycles per core when uops are exectuted in port 1

UOPS_EXECUTED_PORT.PORT_2

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.

UOPS_EXECUTED_PORT.PORT_2_CORE

Cycles per core when uops are dispatched to port 2

UOPS_EXECUTED_PORT.PORT_3

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.

UOPS_EXECUTED_PORT.PORT_3_CORE

Cycles per core when uops are dispatched to port 3

UOPS_EXECUTED_PORT.PORT_4

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.

UOPS_EXECUTED_PORT.PORT_4_CORE

Cycles per core when uops are exectuted in port 4

UOPS_EXECUTED_PORT.PORT_5

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.

UOPS_EXECUTED_PORT.PORT_5_CORE

Cycles per core when uops are exectuted in port 5

UOPS_EXECUTED_PORT.PORT_6

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.

UOPS_EXECUTED_PORT.PORT_6_CORE

Cycles per core when uops are exectuted in port 6

UOPS_EXECUTED_PORT.PORT_7

This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.

UOPS_EXECUTED_PORT.PORT_7_CORE

Cycles per core when uops are dispatched to port 7

UOPS_ISSUED.ANY

This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).

UOPS_ISSUED.FLAGS_MERGE

Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.

UOPS_ISSUED.SINGLE_MUL

Number of Multiply packed/scalar single precision uops allocated

UOPS_ISSUED.SLOW_LEA

Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.

UOPS_ISSUED.STALL_CYCLES

This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.

UOPS_RETIRED.ALL

This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.

UOPS_RETIRED.ALL_PS

This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.

UOPS_RETIRED.RETIRE_SLOTS

This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used.

UOPS_RETIRED.RETIRE_SLOTS_PS

This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.

UOPS_RETIRED.STALL_CYCLES

This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.

UOPS_RETIRED.TOTAL_CYCLES

Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.

UOP_DISPATCHES_CANCELLED.SIMD_PRF

This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.