Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help

Events for Intel® Microarchitecture Code Name Bonnel

This section provides reference for hardware events that can be monitored for the CPU(s):

The following performance-monitoring events are supported:

BACLEARS.ANY

BACLEARS asserted.

BOGUS_BR

Bogus branches

BR_INST_DECODED

Branch instructions decoded

BR_INST_RETIRED.ANY

Retired branch instructions.

BR_INST_RETIRED.ANY1

Retired branch instructions.

BR_INST_RETIRED.MISPRED

Retired mispredicted branch instructions (precise event).

BR_INST_RETIRED.MISPRED.PS

Retired mispredicted branch instructions.

BR_INST_RETIRED.MISPRED_NOT_TAKEN

Retired branch instructions that were mispredicted not-taken.

BR_INST_RETIRED.MISPRED_TAKEN

Retired branch instructions that were mispredicted taken.

BR_INST_RETIRED.PRED_NOT_TAKEN

Retired branch instructions that were predicted not-taken.

BR_INST_RETIRED.PRED_TAKEN

Retired branch instructions that were predicted taken.

BR_INST_RETIRED.TAKEN

Retired taken branch instructions.

BR_INST_TYPE_RETIRED.COND

All macro conditional branch instructions.

BR_INST_TYPE_RETIRED.COND_TAKEN

Only taken macro conditional branch instructions

BR_INST_TYPE_RETIRED.DIR_CALL

All non-indirect calls

BR_INST_TYPE_RETIRED.IND

All indirect branches that are not calls.

BR_INST_TYPE_RETIRED.IND_CALL

All indirect calls, including both register and memory indirect.

BR_INST_TYPE_RETIRED.RET

All indirect branches that have a return mnemonic

BR_INST_TYPE_RETIRED.UNCOND

All macro unconditional branch instructions, excluding calls and indirects

BR_MISSP_TYPE_RETIRED.COND

Mispredicted cond branch instructions retired

BR_MISSP_TYPE_RETIRED.COND_TAKEN

Mispredicted and taken cond branch instructions retired

BR_MISSP_TYPE_RETIRED.IND

Mispredicted ind branches that are not calls

BR_MISSP_TYPE_RETIRED.IND_CALL

Mispredicted indirect calls, including both register and memory indirect.

BR_MISSP_TYPE_RETIRED.RETURN

Mispredicted return branches

BUSQ_EMPTY.SELF

Bus queue is empty.

BUS_BNR_DRV.ALL_AGENTS

Number of Bus Not Ready signals asserted.

BUS_BNR_DRV.THIS_AGENT

Number of Bus Not Ready signals asserted.

BUS_DATA_RCV.SELF

Bus cycles while processor receives data.

BUS_DRDY_CLOCKS.ALL_AGENTS

Bus cycles when data is sent on the bus.

BUS_DRDY_CLOCKS.THIS_AGENT

Bus cycles when data is sent on the bus.

BUS_HITM_DRV.ALL_AGENTS

HITM signal asserted.

BUS_HITM_DRV.THIS_AGENT

HITM signal asserted.

BUS_HIT_DRV.ALL_AGENTS

HIT signal asserted.

BUS_HIT_DRV.THIS_AGENT

HIT signal asserted.

BUS_IO_WAIT.SELF

IO requests waiting in the bus queue.

BUS_LOCK_CLOCKS.ALL_AGENTS

Bus cycles when a LOCK signal is asserted.

BUS_LOCK_CLOCKS.SELF

Bus cycles when a LOCK signal is asserted.

BUS_REQUEST_OUTSTANDING.ALL_AGENTS

Outstanding cacheable data read bus requests duration.

BUS_REQUEST_OUTSTANDING.SELF

Outstanding cacheable data read bus requests duration.

BUS_TRANS_ANY.ALL_AGENTS

All bus transactions.

BUS_TRANS_ANY.SELF

All bus transactions.

BUS_TRANS_BRD.ALL_AGENTS

Burst read bus transactions.

BUS_TRANS_BRD.SELF

Burst read bus transactions.

BUS_TRANS_BURST.ALL_AGENTS

Burst (full cache-line) bus transactions.

BUS_TRANS_BURST.SELF

Burst (full cache-line) bus transactions.

BUS_TRANS_DEF.ALL_AGENTS

Deferred bus transactions.

BUS_TRANS_DEF.SELF

Deferred bus transactions.

BUS_TRANS_IFETCH.ALL_AGENTS

Instruction-fetch bus transactions.

BUS_TRANS_IFETCH.SELF

Instruction-fetch bus transactions.

BUS_TRANS_INVAL.ALL_AGENTS

Invalidate bus transactions.

BUS_TRANS_INVAL.SELF

Invalidate bus transactions.

BUS_TRANS_IO.ALL_AGENTS

IO bus transactions.

BUS_TRANS_IO.SELF

IO bus transactions.

BUS_TRANS_MEM.ALL_AGENTS

Memory bus transactions.

BUS_TRANS_MEM.SELF

Memory bus transactions.

BUS_TRANS_P.ALL_AGENTS

Partial bus transactions.

BUS_TRANS_P.SELF

Partial bus transactions.

BUS_TRANS_PWR.ALL_AGENTS

Partial write bus transaction.

BUS_TRANS_PWR.SELF

Partial write bus transaction.

BUS_TRANS_RFO.ALL_AGENTS

RFO bus transactions.

BUS_TRANS_RFO.SELF

RFO bus transactions.

BUS_TRANS_WB.ALL_AGENTS

Explicit writeback bus transactions.

BUS_TRANS_WB.SELF

Explicit writeback bus transactions.

CPU_CLK_UNHALTED.BUS

Bus cycles when core is not halted

CPU_CLK_UNHALTED.CORE

Core cycles when core is not halted

CPU_CLK_UNHALTED.CORE_P

Core cycles when core is not halted

CPU_CLK_UNHALTED.REF

Reference cycles when core is not halted.

CYCLES_DIV_BUSY

Cycles the divider is busy.

CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED

Cycles during which instruction fetches are stalled.

CYCLES_INT_MASKED.CYCLES_INT_MASKED

Cycles during which interrupts are disabled.

CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED

Cycles during which interrupts are pending and disabled.

DATA_TLB_MISSES.DTLB_MISS

Memory accesses that missed the DTLB.

DATA_TLB_MISSES.DTLB_MISS_LD

DTLB misses due to load operations.

DATA_TLB_MISSES.DTLB_MISS_ST

DTLB misses due to store operations.

DATA_TLB_MISSES.L0_DTLB_MISS_LD

L0 DTLB misses due to load operations.

DATA_TLB_MISSES.L0_DTLB_MISS_ST

L0 DTLB misses due to store operations

DECODE_STALL.IQ_FULL

Decode stall due to IQ full

DECODE_STALL.PFB_EMPTY

Decode stall due to PFB empty

DISPATCH_BLOCKED.ANY

Memory cluster signals to block micro-op dispatch for any reason

DIV.AR

Divide operations retired

DIV.S

Divide operations executed.

EIST_TRANS

Number of Enhanced Intel SpeedStep® Technology (EIST) transitions

EXT_SNOOP.ALL_AGENTS.ANY

External snoops.

EXT_SNOOP.ALL_AGENTS.CLEAN

External snoops.

EXT_SNOOP.ALL_AGENTS.HIT

External snoops.

EXT_SNOOP.ALL_AGENTS.HITM

External snoops.

EXT_SNOOP.THIS_AGENT.ANY

External snoops.

EXT_SNOOP.THIS_AGENT.CLEAN

External snoops.

EXT_SNOOP.THIS_AGENT.HIT

External snoops.

EXT_SNOOP.THIS_AGENT.HITM

External snoops.

FP_ASSIST.AR

Floating point assists for retired operations.

FP_ASSIST.S

Floating point assists.

HW_INT_RCV

Hardware interrupts received.

ICACHE.ACCESSES

Instruction fetches.

ICACHE.HIT

Icache hit

ICACHE.MISSES

Icache miss

INST_RETIRED.ANY

Instructions retired.

INST_RETIRED.ANY_P

Instructions retired (precise event).

ITLB.FLUSH

ITLB flushes.

ITLB.HIT

ITLB hits.

ITLB.MISSES

ITLB misses.

L1D_CACHE.ALL_CACHE_REF

L1 Data Cacheable reads and writes

L1D_CACHE.ALL_REF

L1 Data reads and writes

L1D_CACHE.EVICT

Modified cache lines evicted from the L1 data cache

L1D_CACHE.LD

L1 Cacheable Data Reads

L1D_CACHE.REPL

L1 Data line replacements

L1D_CACHE.REPLM

Modified cache lines allocated in the L1 data cache

L1D_CACHE.ST

L1 Cacheable Data Writes

L2_ADS.SELF

Cycles L2 address bus is in use.

L2_DATA_RQSTS.SELF.E_STATE

All data requests from the L1 data cache

L2_DATA_RQSTS.SELF.I_STATE

All data requests from the L1 data cache

L2_DATA_RQSTS.SELF.MESI

All data requests from the L1 data cache

L2_DATA_RQSTS.SELF.M_STATE

All data requests from the L1 data cache

L2_DATA_RQSTS.SELF.S_STATE

All data requests from the L1 data cache

L2_DBUS_BUSY.SELF

Cycles the L2 cache data bus is busy.

L2_DBUS_BUSY_RD.SELF

Cycles the L2 transfers data to the core.

L2_IFETCH.SELF.E_STATE

L2 cacheable instruction fetch requests

L2_IFETCH.SELF.I_STATE

L2 cacheable instruction fetch requests

L2_IFETCH.SELF.MESI

L2 cacheable instruction fetch requests

L2_IFETCH.SELF.M_STATE

L2 cacheable instruction fetch requests

L2_IFETCH.SELF.S_STATE

L2 cacheable instruction fetch requests

L2_LD.SELF.ANY.E_STATE

L2 cache reads

L2_LD.SELF.ANY.I_STATE

L2 cache reads

L2_LD.SELF.ANY.MESI

L2 cache reads

L2_LD.SELF.ANY.M_STATE

L2 cache reads

L2_LD.SELF.ANY.S_STATE

L2 cache reads

L2_LD.SELF.DEMAND.E_STATE

L2 cache reads

L2_LD.SELF.DEMAND.I_STATE

L2 cache reads

L2_LD.SELF.DEMAND.MESI

L2 cache reads

L2_LD.SELF.DEMAND.M_STATE

L2 cache reads

L2_LD.SELF.DEMAND.S_STATE

L2 cache reads

L2_LD.SELF.PREFETCH.E_STATE

L2 cache reads

L2_LD.SELF.PREFETCH.I_STATE

L2 cache reads

L2_LD.SELF.PREFETCH.MESI

L2 cache reads

L2_LD.SELF.PREFETCH.M_STATE

L2 cache reads

L2_LD.SELF.PREFETCH.S_STATE

L2 cache reads

L2_LD_IFETCH.SELF.E_STATE

All read requests from L1 instruction and data caches

L2_LD_IFETCH.SELF.I_STATE

All read requests from L1 instruction and data caches

L2_LD_IFETCH.SELF.MESI

All read requests from L1 instruction and data caches

L2_LD_IFETCH.SELF.M_STATE

All read requests from L1 instruction and data caches

L2_LD_IFETCH.SELF.S_STATE

All read requests from L1 instruction and data caches

L2_LINES_IN.SELF.ANY

L2 cache misses.

L2_LINES_IN.SELF.DEMAND

L2 cache misses.

L2_LINES_IN.SELF.PREFETCH

L2 cache misses.

L2_LINES_OUT.SELF.ANY

L2 cache lines evicted.

L2_LINES_OUT.SELF.DEMAND

L2 cache lines evicted.

L2_LINES_OUT.SELF.PREFETCH

L2 cache lines evicted.

L2_LOCK.SELF.E_STATE

L2 locked accesses

L2_LOCK.SELF.I_STATE

L2 locked accesses

L2_LOCK.SELF.MESI

L2 locked accesses

L2_LOCK.SELF.M_STATE

L2 locked accesses

L2_LOCK.SELF.S_STATE

L2 locked accesses

L2_M_LINES_IN.SELF

L2 cache line modifications.

L2_M_LINES_OUT.SELF.ANY

Modified lines evicted from the L2 cache

L2_M_LINES_OUT.SELF.DEMAND

Modified lines evicted from the L2 cache

L2_M_LINES_OUT.SELF.PREFETCH

Modified lines evicted from the L2 cache

L2_NO_REQ.SELF

Cycles no L2 cache requests are pending

L2_REJECT_BUSQ.SELF.ANY.E_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.ANY.I_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.ANY.MESI

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.ANY.M_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.ANY.S_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.DEMAND.E_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.DEMAND.I_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.DEMAND.MESI

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.DEMAND.M_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.DEMAND.S_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.PREFETCH.MESI

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE

Rejected L2 cache requests

L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE

Rejected L2 cache requests

L2_RQSTS.SELF.ANY.E_STATE

L2 cache requests

L2_RQSTS.SELF.ANY.I_STATE

L2 cache requests

L2_RQSTS.SELF.ANY.MESI

L2 cache requests

L2_RQSTS.SELF.ANY.M_STATE

L2 cache requests

L2_RQSTS.SELF.ANY.S_STATE

L2 cache requests

L2_RQSTS.SELF.DEMAND.E_STATE

L2 cache requests

L2_RQSTS.SELF.DEMAND.I_STATE

L2 cache demand requests from this core that missed the L2

L2_RQSTS.SELF.DEMAND.MESI

L2 cache demand requests from this core

L2_RQSTS.SELF.DEMAND.M_STATE

L2 cache requests

L2_RQSTS.SELF.DEMAND.S_STATE

L2 cache requests

L2_RQSTS.SELF.PREFETCH.E_STATE

L2 cache requests

L2_RQSTS.SELF.PREFETCH.I_STATE

L2 cache requests

L2_RQSTS.SELF.PREFETCH.MESI

L2 cache requests

L2_RQSTS.SELF.PREFETCH.M_STATE

L2 cache requests

L2_RQSTS.SELF.PREFETCH.S_STATE

L2 cache requests

L2_ST.SELF.E_STATE

L2 store requests

L2_ST.SELF.I_STATE

L2 store requests

L2_ST.SELF.MESI

L2 store requests

L2_ST.SELF.M_STATE

L2 store requests

L2_ST.SELF.S_STATE

L2 store requests

MACHINE_CLEARS.SMC

Self-Modifying Code detected.

MACRO_INSTS.ALL_DECODED

All Instructions decoded

MACRO_INSTS.CISC_DECODED

CISC macro instructions decoded

MACRO_INSTS.NON_CISC_DECODED

Non-CISC nacro instructions decoded

MEM_LOAD_RETIRED.DTLB_MISS

Retired loads that miss the DTLB (precise event).

MEM_LOAD_RETIRED.DTLB_MISS.PS

Retired loads that miss the DTLB (precise event).

MEM_LOAD_RETIRED.L2_HIT

Retired loads that hit the L2 cache (precise event).

MEM_LOAD_RETIRED.L2_HIT.PS

Retired loads that hit the L2 cache (precise event).

MEM_LOAD_RETIRED.L2_MISS

Retired loads that miss the L2 cache

MEM_LOAD_RETIRED.L2_MISS.PS

Retired loads that miss the L2 cache (precise event).

MISALIGN_MEM_REF.BUBBLE

Nonzero segbase 1 bubble

MISALIGN_MEM_REF.LD_BUBBLE

Nonzero segbase load 1 bubble

MISALIGN_MEM_REF.LD_SPLIT

Load splits

MISALIGN_MEM_REF.LD_SPLIT.AR

Load splits (At Retirement)

MISALIGN_MEM_REF.RMW_BUBBLE

Nonzero segbase ld-op-st 1 bubble

MISALIGN_MEM_REF.RMW_SPLIT

ld-op-st splits

MISALIGN_MEM_REF.SPLIT

Memory references that cross an 8-byte boundary.

MISALIGN_MEM_REF.SPLIT.AR

Memory references that cross an 8-byte boundary (At Retirement)

MISALIGN_MEM_REF.ST_BUBBLE

Nonzero segbase store 1 bubble

MISALIGN_MEM_REF.ST_SPLIT

Store splits

MISALIGN_MEM_REF.ST_SPLIT.AR

Store splits (Ar Retirement)

MUL.AR

Multiply operations retired

MUL.S

Multiply operations executed.

PAGE_WALKS.CYCLES

Duration of page-walks in core cycles

PAGE_WALKS.D_SIDE_CYCLES

Duration of D-side only page walks

PAGE_WALKS.D_SIDE_WALKS

Number of D-side only page walks

PAGE_WALKS.I_SIDE_CYCLES

Duration of I-Side page walks

PAGE_WALKS.I_SIDE_WALKS

Number of I-Side page walks

PAGE_WALKS.WALKS

Number of page-walks executed.

PREFETCH.HW_PREFETCH

L1 hardware prefetch request

PREFETCH.PREFETCHNTA

Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed

PREFETCH.PREFETCHT0

Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.

PREFETCH.PREFETCHT1

Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.

PREFETCH.PREFETCHT2

Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.

PREFETCH.SOFTWARE_PREFETCH

Any Software prefetch

PREFETCH.SOFTWARE_PREFETCH.AR

Any Software prefetch

PREFETCH.SW_L2

Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed

REISSUE.ANY

Micro-op reissues for any cause

REISSUE.ANY.AR

Micro-op reissues for any cause (At Retirement)

REISSUE.OVERLAP_STORE

Micro-op reissues on a store-load collision

REISSUE.OVERLAP_STORE.AR

Micro-op reissues on a store-load collision (At Retirement)

RESOURCE_STALLS.DIV_BUSY

Cycles issue is stalled due to div busy.

SEGMENT_REG_LOADS.ANY

Number of segment register loads.

SIMD_ASSIST

SIMD assists invoked.

SIMD_COMP_INST_RETIRED.PACKED_SINGLE

Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.

SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE

Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.

SIMD_COMP_INST_RETIRED.SCALAR_SINGLE

Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.

SIMD_INSTR_RETIRED

SIMD Instructions retired.

SIMD_INST_RETIRED.PACKED_SINGLE

Retired Streaming SIMD Extensions (SSE) packed-single instructions.

SIMD_INST_RETIRED.SCALAR_DOUBLE

Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.

SIMD_INST_RETIRED.SCALAR_SINGLE

Retired Streaming SIMD Extensions (SSE) scalar-single instructions.

SIMD_INST_RETIRED.VECTOR

Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.

SIMD_SAT_INSTR_RETIRED

Saturated arithmetic instructions retired.

SIMD_SAT_UOP_EXEC.AR

SIMD saturated arithmetic micro-ops retired.

SIMD_SAT_UOP_EXEC.S

SIMD saturated arithmetic micro-ops executed.

SIMD_UOPS_EXEC.AR

SIMD micro-ops retired (excluding stores).

SIMD_UOPS_EXEC.S

SIMD micro-ops executed (excluding stores).

SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR

SIMD packed arithmetic micro-ops retired

SIMD_UOP_TYPE_EXEC.ARITHMETIC.S

SIMD packed arithmetic micro-ops executed

SIMD_UOP_TYPE_EXEC.LOGICAL.AR

SIMD packed logical micro-ops retired

SIMD_UOP_TYPE_EXEC.LOGICAL.S

SIMD packed logical micro-ops executed

SIMD_UOP_TYPE_EXEC.MUL.AR

SIMD packed multiply micro-ops retired

SIMD_UOP_TYPE_EXEC.MUL.S

SIMD packed multiply micro-ops executed

SIMD_UOP_TYPE_EXEC.PACK.AR

SIMD packed micro-ops retired

SIMD_UOP_TYPE_EXEC.PACK.S

SIMD packed micro-ops executed

SIMD_UOP_TYPE_EXEC.SHIFT.AR

SIMD packed shift micro-ops retired

SIMD_UOP_TYPE_EXEC.SHIFT.S

SIMD packed shift micro-ops executed

SIMD_UOP_TYPE_EXEC.UNPACK.AR

SIMD unpacked micro-ops retired

SIMD_UOP_TYPE_EXEC.UNPACK.S

SIMD unpacked micro-ops executed

SNOOP_STALL_DRV.ALL_AGENTS

Bus stalled for snoops.

SNOOP_STALL_DRV.SELF

Bus stalled for snoops.

STORE_FORWARDS.ANY

All store forwards

STORE_FORWARDS.GOOD

Good store forwards

THERMAL_TRIP

Number of thermal trips

UOPS.MS_CYCLES

This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.

UOPS_RETIRED.ANY

Micro-ops retired.

UOPS_RETIRED.STALLED_CYCLES

Cycles no micro-ops retired.

UOPS_RETIRED.STALLS

Periods no micro-ops retired.

X87_COMP_OPS_EXE.ANY.AR

Floating point computational micro-ops retired.

X87_COMP_OPS_EXE.ANY.S

Floating point computational micro-ops executed.

X87_COMP_OPS_EXE.FXCH.AR

FXCH uops retired.

X87_COMP_OPS_EXE.FXCH.S

FXCH uops executed.