Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help
This section provides reference for hardware events that can be monitored for the CPU(s):
The following performance-monitoring events are supported:
BACLEARS asserted.
Bogus branches
Branch instructions decoded
Retired branch instructions.
Retired branch instructions.
Retired mispredicted branch instructions (precise event).
Retired mispredicted branch instructions.
Retired branch instructions that were mispredicted not-taken.
Retired branch instructions that were mispredicted taken.
Retired branch instructions that were predicted not-taken.
Retired branch instructions that were predicted taken.
Retired taken branch instructions.
All macro conditional branch instructions.
Only taken macro conditional branch instructions
All non-indirect calls
All indirect branches that are not calls.
All indirect calls, including both register and memory indirect.
All indirect branches that have a return mnemonic
All macro unconditional branch instructions, excluding calls and indirects
Mispredicted cond branch instructions retired
Mispredicted and taken cond branch instructions retired
Mispredicted ind branches that are not calls
Mispredicted indirect calls, including both register and memory indirect.
Mispredicted return branches
Bus queue is empty.
Number of Bus Not Ready signals asserted.
Number of Bus Not Ready signals asserted.
Bus cycles while processor receives data.
Bus cycles when data is sent on the bus.
Bus cycles when data is sent on the bus.
HITM signal asserted.
HITM signal asserted.
HIT signal asserted.
HIT signal asserted.
IO requests waiting in the bus queue.
Bus cycles when a LOCK signal is asserted.
Bus cycles when a LOCK signal is asserted.
Outstanding cacheable data read bus requests duration.
Outstanding cacheable data read bus requests duration.
All bus transactions.
All bus transactions.
Burst read bus transactions.
Burst read bus transactions.
Burst (full cache-line) bus transactions.
Burst (full cache-line) bus transactions.
Deferred bus transactions.
Deferred bus transactions.
Instruction-fetch bus transactions.
Instruction-fetch bus transactions.
Invalidate bus transactions.
Invalidate bus transactions.
IO bus transactions.
IO bus transactions.
Memory bus transactions.
Memory bus transactions.
Partial bus transactions.
Partial bus transactions.
Partial write bus transaction.
Partial write bus transaction.
RFO bus transactions.
RFO bus transactions.
Explicit writeback bus transactions.
Explicit writeback bus transactions.
Bus cycles when core is not halted
Core cycles when core is not halted
Core cycles when core is not halted
Reference cycles when core is not halted.
Cycles the divider is busy.
Cycles during which instruction fetches are stalled.
Cycles during which interrupts are disabled.
Cycles during which interrupts are pending and disabled.
Memory accesses that missed the DTLB.
DTLB misses due to load operations.
DTLB misses due to store operations.
L0 DTLB misses due to load operations.
L0 DTLB misses due to store operations
Decode stall due to IQ full
Decode stall due to PFB empty
Memory cluster signals to block micro-op dispatch for any reason
Divide operations retired
Divide operations executed.
Number of Enhanced Intel SpeedStep® Technology (EIST) transitions
External snoops.
External snoops.
External snoops.
External snoops.
External snoops.
External snoops.
External snoops.
External snoops.
Floating point assists for retired operations.
Floating point assists.
Hardware interrupts received.
Instruction fetches.
Icache hit
Icache miss
Instructions retired.
Instructions retired (precise event).
ITLB flushes.
ITLB hits.
ITLB misses.
L1 Data Cacheable reads and writes
L1 Data reads and writes
Modified cache lines evicted from the L1 data cache
L1 Cacheable Data Reads
L1 Data line replacements
Modified cache lines allocated in the L1 data cache
L1 Cacheable Data Writes
Cycles L2 address bus is in use.
All data requests from the L1 data cache
All data requests from the L1 data cache
All data requests from the L1 data cache
All data requests from the L1 data cache
All data requests from the L1 data cache
Cycles the L2 cache data bus is busy.
Cycles the L2 transfers data to the core.
L2 cacheable instruction fetch requests
L2 cacheable instruction fetch requests
L2 cacheable instruction fetch requests
L2 cacheable instruction fetch requests
L2 cacheable instruction fetch requests
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
L2 cache reads
All read requests from L1 instruction and data caches
All read requests from L1 instruction and data caches
All read requests from L1 instruction and data caches
All read requests from L1 instruction and data caches
All read requests from L1 instruction and data caches
L2 cache misses.
L2 cache misses.
L2 cache misses.
L2 cache lines evicted.
L2 cache lines evicted.
L2 cache lines evicted.
L2 locked accesses
L2 locked accesses
L2 locked accesses
L2 locked accesses
L2 locked accesses
L2 cache line modifications.
Modified lines evicted from the L2 cache
Modified lines evicted from the L2 cache
Modified lines evicted from the L2 cache
Cycles no L2 cache requests are pending
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
Rejected L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache demand requests from this core that missed the L2
L2 cache demand requests from this core
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 cache requests
L2 store requests
L2 store requests
L2 store requests
L2 store requests
L2 store requests
Self-Modifying Code detected.
All Instructions decoded
CISC macro instructions decoded
Non-CISC nacro instructions decoded
Retired loads that miss the DTLB (precise event).
Retired loads that miss the DTLB (precise event).
Retired loads that hit the L2 cache (precise event).
Retired loads that hit the L2 cache (precise event).
Retired loads that miss the L2 cache
Retired loads that miss the L2 cache (precise event).
Nonzero segbase 1 bubble
Nonzero segbase load 1 bubble
Load splits
Load splits (At Retirement)
Nonzero segbase ld-op-st 1 bubble
ld-op-st splits
Memory references that cross an 8-byte boundary.
Memory references that cross an 8-byte boundary (At Retirement)
Nonzero segbase store 1 bubble
Store splits
Store splits (Ar Retirement)
Multiply operations retired
Multiply operations executed.
Duration of page-walks in core cycles
Duration of D-side only page walks
Number of D-side only page walks
Duration of I-Side page walks
Number of I-Side page walks
Number of page-walks executed.
L1 hardware prefetch request
Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.
Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.
Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.
Any Software prefetch
Any Software prefetch
Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed
Micro-op reissues for any cause
Micro-op reissues for any cause (At Retirement)
Micro-op reissues on a store-load collision
Micro-op reissues on a store-load collision (At Retirement)
Cycles issue is stalled due to div busy.
Number of segment register loads.
SIMD assists invoked.
Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.
Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.
Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.
SIMD Instructions retired.
Retired Streaming SIMD Extensions (SSE) packed-single instructions.
Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.
Retired Streaming SIMD Extensions (SSE) scalar-single instructions.
Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.
Saturated arithmetic instructions retired.
SIMD saturated arithmetic micro-ops retired.
SIMD saturated arithmetic micro-ops executed.
SIMD micro-ops retired (excluding stores).
SIMD micro-ops executed (excluding stores).
SIMD packed arithmetic micro-ops retired
SIMD packed arithmetic micro-ops executed
SIMD packed logical micro-ops retired
SIMD packed logical micro-ops executed
SIMD packed multiply micro-ops retired
SIMD packed multiply micro-ops executed
SIMD packed micro-ops retired
SIMD packed micro-ops executed
SIMD packed shift micro-ops retired
SIMD packed shift micro-ops executed
SIMD unpacked micro-ops retired
SIMD unpacked micro-ops executed
Bus stalled for snoops.
Bus stalled for snoops.
All store forwards
Good store forwards
Number of thermal trips
This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.
Micro-ops retired.
Cycles no micro-ops retired.
Periods no micro-ops retired.
Floating point computational micro-ops retired.
Floating point computational micro-ops executed.
FXCH uops retired.
FXCH uops executed.