Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help
This section provides reference for hardware events that can be monitored for the CPU(s):
The following performance-monitoring events are supported:
Divide operations executed
Cycles when divider is busy executing divide operations
Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
Speculative and retired branches
Speculative and retired macro-conditional branches
Speculative and retired macro-unconditional branches excluding calls and indirects
Speculative and retired direct near calls
Speculative and retired indirect branches excluding calls and returns
Speculative and retired indirect return branches.
Not taken macro-conditional branches
Taken speculative and retired macro-conditional branches
Taken speculative and retired macro-conditional branch instructions excluding calls and indirects
Taken speculative and retired direct near calls
Taken speculative and retired indirect branches excluding calls and returns
Taken speculative and retired indirect calls
Taken speculative and retired indirect branches with return mnemonic
All (macro) branch instructions retired.
All (macro) branch instructions retired.
Conditional branch instructions retired.
Conditional branch instructions retired.
Far branch instructions retired.
Direct and indirect near call instructions retired.
Direct and indirect near call instructions retired.
Direct and indirect macro near call instructions retired (captured in ring 3).
Direct and indirect macro near call instructions retired (captured in ring 3).
Return instructions retired.
Return instructions retired.
Taken branch instructions retired.
Taken branch instructions retired.
Not taken branch instructions retired.
Speculative and retired mispredicted macro conditional branches
Speculative and retired mispredicted macro conditional branches
Mispredicted indirect branches excluding calls and returns
Not taken speculative and retired mispredicted macro conditional branches
Taken speculative and retired mispredicted macro conditional branches
Taken speculative and retired mispredicted indirect branches excluding calls and returns
Taken speculative and retired mispredicted indirect calls
Taken speculative and retired mispredicted indirect branches with return mnemonic
All mispredicted macro branch instructions retired.
Mispredicted macro branch instructions retired.
Mispredicted conditional branch instructions retired.
Mispredicted conditional branch instructions retired.
number of near branch instructions retired that were mispredicted and taken.
number of near branch instructions retired that were mispredicted and taken.
Unhalted core cycles when the thread is in ring 0
Number of intervals between processor halts while thread is in ring 0
Unhalted core cycles when thread is in rings 1, 2, or 3
Count XClk pulses when this thread is unhalted and the other is halted.
Cases when the core is unhalted at 100 Mhz
Reference cycles when the core is not in halt state.
Core cycles when the core is not in halt state.
Thread cycles when thread is not in halt state
Cycles with pending L1 cache miss loads.
Cycles with pending L2 cache miss loads.
Cycles with pending memory loads.
Total execution stalls
Execution stalls due to L1 data cache misses
Execution stalls due to L2 cache misses.
Execution stalls due to memory subsystem.
Decode Stream Buffer (DSB)-to-MITE switches
Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles
Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines
Page walk for a large page completed for Demand load
Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.
Load operations that miss the first DTLB level but hit the second and do not cause page walks
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.
Demand load cycles page miss handler (PMH) is busy with this walk.
Store misses in all DTLB levels that cause page walks
Store operations that miss the first TLB level but hit the second and do not cause page walks
Store misses in all DTLB levels that cause completed page walks
Cycles when PMH is busy with page walks
Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
Cycles with any input/output SSE or FP assist
Number of SIMD FP assists due to input values
Number of SIMD FP assists due to Output values
Number of X87 assists due to input value.
Number of X87 assists due to output value.
Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle
Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle
Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle
Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle
Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s
Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches
Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss
Instruction cache, streaming buffer and victim cache misses
Cycles Decode Stream Buffer (DSB) is delivering 4 Uops
Cycles Decode Stream Buffer (DSB) is delivering any Uop
Cycles MITE is delivering 4 Uops
Cycles MITE is delivering any Uop
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path
Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path
Instruction Decode Queue (IDQ) empty cycles
Uops delivered to Instruction Decode Queue (IDQ) from MITE path
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path
Uops delivered to Instruction Decode Queue (IDQ) from MITE path
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy
Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer
Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled
Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
Cycles with less than 2 uops delivered by the front end.
Cycles with less than 3 uops delivered by the front end.
Stall cycles because IQ is full
Stalls caused by changing prefix length of the instruction.
Instructions retired from execution.
Number of instructions retired. General Counter - architectural event
Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution
Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)
Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)
Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.
Completed page walks in ITLB due to STLB load misses for large pages
Misses at all ITLB levels that cause page walks
Operations that miss the first ITLB level but hit the second and do not cause any page walks
Misses in all ITLB levels that cause completed page walks
Cycles when PMH is busy with page walks
L1D data line replacements
L1D miss oustandings duration in cycles
Cycles with L1D load Misses outstanding.
Not rejected writebacks from L1D to L2 cache lines in any state.
Not rejected writebacks from L1D to L2 cache lines in E state
Not rejected writebacks from L1D to L2 cache lines in M state
Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)
L2 cache lines filling L2
L2 cache lines in E state filling L2
L2 cache lines in I state filling L2
L2 cache lines in S state filling L2
Clean L2 cache lines evicted by demand
Dirty L2 cache lines evicted by demand
Dirty L2 cache lines filling the L2
Clean L2 cache lines evicted by L2 prefetch
Dirty L2 cache lines evicted by L2 prefetch
L2 code requests
Demand Data Read requests
Requests from L2 hardware prefetchers
RFO requests to L2 cache
L2 cache hits when fetching instructions, code reads.
L2 cache misses when fetching instructions
Demand Data Read requests that hit L2 cache
Requests from the L2 hardware prefetchers that hit L2 cache
Requests from the L2 hardware prefetchers that miss L2 cache
RFO requests that hit L2 cache
RFO requests that miss L2 cache
RFOs that access cache lines in any state
RFOs that hit cache lines in M state
RFOs that miss cache lines
L2 or LLC HW prefetches that access L2 cache
Transactions accessing L2 pipe
L2 cache accesses when fetching instructions
Demand Data Read requests that access L2 cache
L1D writebacks that access L2 cache
L2 fill requests that access L2 cache
L2 writebacks that access L2 cache
RFO requests that access L2 cache
This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
Cases when loads get true Block-on-Store blocking code preventing store forwarding
False dependencies in MOB due to partial compare on address
Not software-prefetch load dispatches that hit FB allocated for hardware prefetch
Not software-prefetch load dispatches that hit FB allocated for software prefetch
Cycles when L1D is locked
Cycles when L1 and L2 are locked due to UC or split lock
Core-originated cacheable demand requests missed LLC
Core-originated cacheable demand requests that refer to LLC
Cycles 4 Uops delivered by the LSD, but didn't come from the decoder
Cycles Uops delivered by the LSD, but didn't come from the decoder
Number of Uops delivered by the LSD.
Number of machine clears (nukes) of any type.
This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
Counts the number of machine clears due to memory order conflicts.
Self-modifying code (SMC) detected.
Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.
Retired load uops which data sources were HitM responses from shared LLC.
Retired load uops which data sources were HitM responses from shared LLC.
Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.
Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
Retired load uops which data sources were hits in LLC without snoops required.
Retired load uops which data sources were hits in LLC without snoops required.
Retired load uops which data sources missed LLC but serviced from local dram.
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
Retired load uops with L1 cache hits as data sources.
Retired load uops with L1 cache hits as data sources.
Retired load uops which data sources following L1 data-cache miss
Retired load uops which data sources following L1 data-cache miss.
Retired load uops with L2 cache hits as data sources.
Retired load uops with L2 cache hits as data sources.
Miss in mid-level (L2) cache. Excludes Unknown data-source.
Retired load uops with L2 cache misses as data sources.
Retired load uops which data sources were data hits in LLC without snoops required.
Retired load uops which data sources were data hits in LLC without snoops required.
Miss in last-level (L3) cache. Excludes Unknown data-source.
Miss in last-level (L3) cache. Excludes Unknown data-source.
Loads with latency value being above 128
Loads with latency value being above 16
Loads with latency value being above 256
Loads with latency value being above 32
Loads with latency value being above 4
Loads with latency value being above 512
Loads with latency value being above 64
Loads with latency value being above 8
Sample stores and collect precise store operation via PEBS record. PMC3 only.
Load uops retired to architected path with filter on bits 0 and 1 applied.
Load uops retired to architected path with filter on bits 0 and 1 applied.
Store uops retired to architected path with filter on bits 0 and 1 applied.
Store uops retired to architected path with filter on bits 0 and 1 applied.
Load uops with locked access retired to architected path.
Load uops with locked access retired to architected path.
Line-splitted load uops retired to architected path.
Line-splitted load uops retired to architected path.
Line-splitted store uops retired to architected path.
Line-splitted store uops retired to architected path.
Load uops with true STLB miss retired to architected path.
Load uops with true STLB miss retired to architected path.
Store uops with true STLB miss retired to architected path.
Store uops true STLB miss retired to architected path.
Speculative cache line split load uops dispatched to L1 cache
Speculative cache line split STA uops dispatched to L1 cache
Number of integer Move Elimination candidate uops that were eliminated.
Number of integer Move Elimination candidate uops that were not eliminated.
Number of SIMD Move Elimination candidate uops that were eliminated.
Number of SIMD Move Elimination candidate uops that were not eliminated.
Demand and prefetch data reads
Cacheable and noncachaeble code read requests
Demand Data Read requests sent to uncore
Demand RFO requests including regular RFOs, locks, ItoM
Cases when offcore requests buffer cannot take more entries for core
Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore
Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore
Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle
Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore
Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle
Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle
Offcore outstanding Demand Data Read transactions in uncore queue.
Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore
Counts all demand & prefetch code reads that hit in the LLC
Counts all demand & prefetch code reads that hit in the LLC
Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand & prefetch code reads that miss the LLC and the data returned from dram
Counts all demand & prefetch code reads that miss the LLC and the data returned from dram
Counts all demand & prefetch data reads
Counts all demand & prefetch data reads
Counts all demand & prefetch data reads that hit in the LLC
Counts all demand & prefetch data reads that hit in the LLC
Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand & prefetch data reads that miss the LLC and the data returned from dram
Counts all demand & prefetch data reads that miss the LLC and the data returned from dram
Counts all prefetch RFOs that hit in the LLC
Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all data/code/rfo references (demand & prefetch)
Counts all data/code/rfo references (demand & prefetch)
Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram
Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram
Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC
Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC
Counts all demand & prefetch prefetch RFOs
Counts all demand & prefetch prefetch RFOs
Counts all demand & prefetch RFOs that hit in the LLC
Counts all demand & prefetch RFOs that hit in the LLC
Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all writebacks from the core to the LLC
Counts all writebacks from the core to the LLC
Counts LLC replacements
Counts LLC replacements
Counts all demand code reads
Counts all demand code reads
Counts all demand code reads that hit in the LLC
Counts all demand code reads that hit in the LLC
Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand code reads that miss the LLC and the data returned from dram
Counts demand code reads that miss the LLC and the data returned from dram
Counts all demand data reads
Counts all demand data reads
Counts all demand data reads that hit in the LLC
Counts all demand data reads that hit in the LLC
Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data reads that miss the LLC and the data returned from dram
Counts demand data reads that miss the LLC and the data returned from dram
Counts all demand rfo's
Counts all demand rfo's
Counts all demand data writes (RFOs) that hit in the LLC
Counts all demand data writes (RFOs) that hit in the LLC
Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches
Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches
Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses
Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address
Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address
Counts non-temporal stores
Counts non-temporal stores
Number of times any microcode assist is invoked by HW upon uop writeback.
Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.
Number of transitions from AVX-256 to legacy SSE when penalty applicable.
Number of transitions from SSE to AVX-256 when penalty applicable.
Number of any page walk that had a miss in LLC.
Resource-related stall cycles
Cycles stalled due to re-order buffer full.
Cycles stalled due to no eligible RS entry available.
Cycles stalled due to no store buffers available. (not including draining form sync).
Count cases of saving new LBR
Cycles when Reservation Station (RS) is empty for the thread
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
number of AVX-256 Computational FP double precision uops issued this cycle
number of GSSE-256 Computational FP single precision uops issued this cycle
DTLB flush attempts of the thread-specific entries
STLB flush attempts
Cycles weighted by number of requests pending in Coherency Tracker.
Number of requests allocated in Coherency Tracker.
Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.
Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.
Counts the number of LLC evictions allocated.
Counts the number of allocated write entries, include full, partial, and LLC evictions.
Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.
LLC lookup request that access cache and found line in E-state.
Filter on external snoop requests.
LLC lookup request that access cache and found line in I-state.
LLC lookup request that access cache and found line in M-state.
Filter on processor core initiated cacheable read requests.
LLC lookup request that access cache and found line in S-state.
Filter on processor core initiated cacheable write requests.
Filter on cross-core snoops initiated by this Cbox due to LLC eviction.
Filter on cross-core snoops initiated by this Cbox due to external snoop request.
A snoop hits a non-modified line in some processor core
A snoop hits a modified line in some processor core.
A snoop invalidates a non-modified line in some processor core
A snoop invalidates a modified line in some processor core
A snoop misses in some processor core.
Filter on cross-core snoops initiated by this Cbox due to processor core memory request.
This 48-bit fixed counter counts the UCLK cycles
Cycles per thread when uops are dispatched to port 0
Cycles per core when uops are dispatched to port 0
Cycles per thread when uops are dispatched to port 1
Cycles per core when uops are dispatched to port 1
Cycles per thread when load or STA uops are dispatched to port 2
Uops dispatched to port 2, loads and stores per core (speculative and retired)
Cycles per thread when load or STA uops are dispatched to port 3
Cycles per core when load or STA uops are dispatched to port 3
Cycles per thread when uops are dispatched to port 4
Cycles per core when uops are dispatched to port 4
Cycles per thread when uops are dispatched to port 5
Cycles per core when uops are dispatched to port 5
Number of uops executed on the core.
Cycles where at least 1 uop was executed per-thread
Cycles where at least 2 uops were executed per-thread
Cycles where at least 3 uops were executed per-thread
Cycles where at least 4 uops were executed per-thread
Counts number of cycles no uops were dispatched to be executed on this thread.
Counts the number of uops to be executed per-thread each cycle.
Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads
Number of flags-merge uops being allocated.
Number of Multiply packed/scalar single precision uops allocated
Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread
Actually retired uops.
Retired uops.
Cycles without actually retired uops.
Retirement slots used.
Retirement slots used.
Cycles without actually retired uops.
Cycles with less than 10 actually retired uops.