Intel® VTune™ Amplifier XE and Intel® VTune™ Amplifier for Systems Help

Events for Intel® Microarchitecture Code Name Ivy Bridge

This section provides reference for hardware events that can be monitored for the CPU(s):

The following performance-monitoring events are supported:

ARITH.FPU_DIV

Divide operations executed

ARITH.FPU_DIV_ACTIVE

Cycles when divider is busy executing divide operations

BACLEARS.ANY

Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.

BR_INST_EXEC.ALL_BRANCHES

Speculative and retired branches

BR_INST_EXEC.ALL_CONDITIONAL

Speculative and retired macro-conditional branches

BR_INST_EXEC.ALL_DIRECT_JMP

Speculative and retired macro-unconditional branches excluding calls and indirects

BR_INST_EXEC.ALL_DIRECT_NEAR_CALL

Speculative and retired direct near calls

BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET

Speculative and retired indirect branches excluding calls and returns

BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN

Speculative and retired indirect return branches.

BR_INST_EXEC.NONTAKEN_CONDITIONAL

Not taken macro-conditional branches

BR_INST_EXEC.TAKEN_CONDITIONAL

Taken speculative and retired macro-conditional branches

BR_INST_EXEC.TAKEN_DIRECT_JUMP

Taken speculative and retired macro-conditional branch instructions excluding calls and indirects

BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL

Taken speculative and retired direct near calls

BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET

Taken speculative and retired indirect branches excluding calls and returns

BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL

Taken speculative and retired indirect calls

BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN

Taken speculative and retired indirect branches with return mnemonic

BR_INST_RETIRED.ALL_BRANCHES

All (macro) branch instructions retired.

BR_INST_RETIRED.ALL_BRANCHES_PS

All (macro) branch instructions retired.

BR_INST_RETIRED.CONDITIONAL

Conditional branch instructions retired.

BR_INST_RETIRED.CONDITIONAL_PS

Conditional branch instructions retired.

BR_INST_RETIRED.FAR_BRANCH

Far branch instructions retired.

BR_INST_RETIRED.NEAR_CALL

Direct and indirect near call instructions retired.

BR_INST_RETIRED.NEAR_CALL_PS

Direct and indirect near call instructions retired.

BR_INST_RETIRED.NEAR_CALL_R3

Direct and indirect macro near call instructions retired (captured in ring 3).

BR_INST_RETIRED.NEAR_CALL_R3_PS

Direct and indirect macro near call instructions retired (captured in ring 3).

BR_INST_RETIRED.NEAR_RETURN

Return instructions retired.

BR_INST_RETIRED.NEAR_RETURN_PS

Return instructions retired.

BR_INST_RETIRED.NEAR_TAKEN

Taken branch instructions retired.

BR_INST_RETIRED.NEAR_TAKEN_PS

Taken branch instructions retired.

BR_INST_RETIRED.NOT_TAKEN

Not taken branch instructions retired.

BR_MISP_EXEC.ALL_BRANCHES

Speculative and retired mispredicted macro conditional branches

BR_MISP_EXEC.ALL_CONDITIONAL

Speculative and retired mispredicted macro conditional branches

BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET

Mispredicted indirect branches excluding calls and returns

BR_MISP_EXEC.NONTAKEN_CONDITIONAL

Not taken speculative and retired mispredicted macro conditional branches

BR_MISP_EXEC.TAKEN_CONDITIONAL

Taken speculative and retired mispredicted macro conditional branches

BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET

Taken speculative and retired mispredicted indirect branches excluding calls and returns

BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL

Taken speculative and retired mispredicted indirect calls

BR_MISP_EXEC.TAKEN_RETURN_NEAR

Taken speculative and retired mispredicted indirect branches with return mnemonic

BR_MISP_RETIRED.ALL_BRANCHES

All mispredicted macro branch instructions retired.

BR_MISP_RETIRED.ALL_BRANCHES_PS

Mispredicted macro branch instructions retired.

BR_MISP_RETIRED.CONDITIONAL

Mispredicted conditional branch instructions retired.

BR_MISP_RETIRED.CONDITIONAL_PS

Mispredicted conditional branch instructions retired.

BR_MISP_RETIRED.NEAR_TAKEN

number of near branch instructions retired that were mispredicted and taken.

BR_MISP_RETIRED.NEAR_TAKEN_PS

number of near branch instructions retired that were mispredicted and taken.

CPL_CYCLES.RING0

Unhalted core cycles when the thread is in ring 0

CPL_CYCLES.RING0_TRANS

Number of intervals between processor halts while thread is in ring 0

CPL_CYCLES.RING123

Unhalted core cycles when thread is in rings 1, 2, or 3

CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE

Count XClk pulses when this thread is unhalted and the other is halted.

CPU_CLK_THREAD_UNHALTED.REF_XCLK

Cases when the core is unhalted at 100 Mhz

CPU_CLK_UNHALTED.REF_TSC

Reference cycles when the core is not in halt state.

CPU_CLK_UNHALTED.THREAD

Core cycles when the core is not in halt state.

CPU_CLK_UNHALTED.THREAD_P

Thread cycles when thread is not in halt state

CYCLE_ACTIVITY.CYCLES_L1D_PENDING

Cycles with pending L1 cache miss loads.

CYCLE_ACTIVITY.CYCLES_L2_PENDING

Cycles with pending L2 cache miss loads.

CYCLE_ACTIVITY.CYCLES_LDM_PENDING

Cycles with pending memory loads.

CYCLE_ACTIVITY.CYCLES_NO_EXECUTE

Total execution stalls

CYCLE_ACTIVITY.STALLS_L1D_PENDING

Execution stalls due to L1 data cache misses

CYCLE_ACTIVITY.STALLS_L2_PENDING

Execution stalls due to L2 cache misses.

CYCLE_ACTIVITY.STALLS_LDM_PENDING

Execution stalls due to memory subsystem.

DSB2MITE_SWITCHES.COUNT

Decode Stream Buffer (DSB)-to-MITE switches

DSB2MITE_SWITCHES.PENALTY_CYCLES

Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles

DSB_FILL.EXCEED_DSB_LINES

Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines

DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED

Page walk for a large page completed for Demand load

DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK

Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.

DTLB_LOAD_MISSES.STLB_HIT

Load operations that miss the first DTLB level but hit the second and do not cause page walks

DTLB_LOAD_MISSES.WALK_COMPLETED

Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.

DTLB_LOAD_MISSES.WALK_DURATION

Demand load cycles page miss handler (PMH) is busy with this walk.

DTLB_STORE_MISSES.MISS_CAUSES_A_WALK

Store misses in all DTLB levels that cause page walks

DTLB_STORE_MISSES.STLB_HIT

Store operations that miss the first TLB level but hit the second and do not cause page walks

DTLB_STORE_MISSES.WALK_COMPLETED

Store misses in all DTLB levels that cause completed page walks

DTLB_STORE_MISSES.WALK_DURATION

Cycles when PMH is busy with page walks

EPT.WALK_CYCLES

Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.

FP_ASSIST.ANY

Cycles with any input/output SSE or FP assist

FP_ASSIST.SIMD_INPUT

Number of SIMD FP assists due to input values

FP_ASSIST.SIMD_OUTPUT

Number of SIMD FP assists due to Output values

FP_ASSIST.X87_INPUT

Number of X87 assists due to input value.

FP_ASSIST.X87_OUTPUT

Number of X87 assists due to output value.

FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE

Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle

FP_COMP_OPS_EXE.SSE_PACKED_SINGLE

Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle

FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE

Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle

FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE

Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle

FP_COMP_OPS_EXE.X87

Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s

ICACHE.HIT

Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches

ICACHE.IFETCH_STALL

Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss

ICACHE.MISSES

Instruction cache, streaming buffer and victim cache misses

IDQ.ALL_DSB_CYCLES_4_UOPS

Cycles Decode Stream Buffer (DSB) is delivering 4 Uops

IDQ.ALL_DSB_CYCLES_ANY_UOPS

Cycles Decode Stream Buffer (DSB) is delivering any Uop

IDQ.ALL_MITE_CYCLES_4_UOPS

Cycles MITE is delivering 4 Uops

IDQ.ALL_MITE_CYCLES_ANY_UOPS

Cycles MITE is delivering any Uop

IDQ.DSB_CYCLES

Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path

IDQ.DSB_UOPS

Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path

IDQ.EMPTY

Instruction Decode Queue (IDQ) empty cycles

IDQ.MITE_ALL_UOPS

Uops delivered to Instruction Decode Queue (IDQ) from MITE path

IDQ.MITE_CYCLES

Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path

IDQ.MITE_UOPS

Uops delivered to Instruction Decode Queue (IDQ) from MITE path

IDQ.MS_CYCLES

Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy

IDQ.MS_DSB_CYCLES

Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy

IDQ.MS_DSB_OCCUR

Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy

IDQ.MS_DSB_UOPS

Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy

IDQ.MS_MITE_UOPS

Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy

IDQ.MS_SWITCHES

Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer

IDQ.MS_UOPS

Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy

IDQ_UOPS_NOT_DELIVERED.CORE

Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled

IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE

Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled

IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK

Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE

Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE

Cycles with less than 2 uops delivered by the front end.

IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE

Cycles with less than 3 uops delivered by the front end.

ILD_STALL.IQ_FULL

Stall cycles because IQ is full

ILD_STALL.LCP

Stalls caused by changing prefix length of the instruction.

INST_RETIRED.ANY

Instructions retired from execution.

INST_RETIRED.ANY_P

Number of instructions retired. General Counter - architectural event

INST_RETIRED.PREC_DIST

Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution

INT_MISC.RECOVERY_CYCLES

Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)

INT_MISC.RECOVERY_STALLS_COUNT

Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)

ITLB.ITLB_FLUSH

Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.

ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED

Completed page walks in ITLB due to STLB load misses for large pages

ITLB_MISSES.MISS_CAUSES_A_WALK

Misses at all ITLB levels that cause page walks

ITLB_MISSES.STLB_HIT

Operations that miss the first ITLB level but hit the second and do not cause any page walks

ITLB_MISSES.WALK_COMPLETED

Misses in all ITLB levels that cause completed page walks

ITLB_MISSES.WALK_DURATION

Cycles when PMH is busy with page walks

L1D.REPLACEMENT

L1D data line replacements

L1D_PEND_MISS.PENDING

L1D miss oustandings duration in cycles

L1D_PEND_MISS.PENDING_CYCLES

Cycles with L1D load Misses outstanding.

L2_L1D_WB_RQSTS.ALL

Not rejected writebacks from L1D to L2 cache lines in any state.

L2_L1D_WB_RQSTS.HIT_E

Not rejected writebacks from L1D to L2 cache lines in E state

L2_L1D_WB_RQSTS.HIT_M

Not rejected writebacks from L1D to L2 cache lines in M state

L2_L1D_WB_RQSTS.MISS

Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)

L2_LINES_IN.ALL

L2 cache lines filling L2

L2_LINES_IN.E

L2 cache lines in E state filling L2

L2_LINES_IN.I

L2 cache lines in I state filling L2

L2_LINES_IN.S

L2 cache lines in S state filling L2

L2_LINES_OUT.DEMAND_CLEAN

Clean L2 cache lines evicted by demand

L2_LINES_OUT.DEMAND_DIRTY

Dirty L2 cache lines evicted by demand

L2_LINES_OUT.DIRTY_ALL

Dirty L2 cache lines filling the L2

L2_LINES_OUT.PF_CLEAN

Clean L2 cache lines evicted by L2 prefetch

L2_LINES_OUT.PF_DIRTY

Dirty L2 cache lines evicted by L2 prefetch

L2_RQSTS.ALL_CODE_RD

L2 code requests

L2_RQSTS.ALL_DEMAND_DATA_RD

Demand Data Read requests

L2_RQSTS.ALL_PF

Requests from L2 hardware prefetchers

L2_RQSTS.ALL_RFO

RFO requests to L2 cache

L2_RQSTS.CODE_RD_HIT

L2 cache hits when fetching instructions, code reads.

L2_RQSTS.CODE_RD_MISS

L2 cache misses when fetching instructions

L2_RQSTS.DEMAND_DATA_RD_HIT

Demand Data Read requests that hit L2 cache

L2_RQSTS.PF_HIT

Requests from the L2 hardware prefetchers that hit L2 cache

L2_RQSTS.PF_MISS

Requests from the L2 hardware prefetchers that miss L2 cache

L2_RQSTS.RFO_HIT

RFO requests that hit L2 cache

L2_RQSTS.RFO_MISS

RFO requests that miss L2 cache

L2_STORE_LOCK_RQSTS.ALL

RFOs that access cache lines in any state

L2_STORE_LOCK_RQSTS.HIT_M

RFOs that hit cache lines in M state

L2_STORE_LOCK_RQSTS.MISS

RFOs that miss cache lines

L2_TRANS.ALL_PF

L2 or LLC HW prefetches that access L2 cache

L2_TRANS.ALL_REQUESTS

Transactions accessing L2 pipe

L2_TRANS.CODE_RD

L2 cache accesses when fetching instructions

L2_TRANS.DEMAND_DATA_RD

Demand Data Read requests that access L2 cache

L2_TRANS.L1D_WB

L1D writebacks that access L2 cache

L2_TRANS.L2_FILL

L2 fill requests that access L2 cache

L2_TRANS.L2_WB

L2 writebacks that access L2 cache

L2_TRANS.RFO

RFO requests that access L2 cache

LD_BLOCKS.NO_SR

This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.

LD_BLOCKS.STORE_FORWARD

Cases when loads get true Block-on-Store blocking code preventing store forwarding

LD_BLOCKS_PARTIAL.ADDRESS_ALIAS

False dependencies in MOB due to partial compare on address

LOAD_HIT_PRE.HW_PF

Not software-prefetch load dispatches that hit FB allocated for hardware prefetch

LOAD_HIT_PRE.SW_PF

Not software-prefetch load dispatches that hit FB allocated for software prefetch

LOCK_CYCLES.CACHE_LOCK_DURATION

Cycles when L1D is locked

LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION

Cycles when L1 and L2 are locked due to UC or split lock

LONGEST_LAT_CACHE.MISS

Core-originated cacheable demand requests missed LLC

LONGEST_LAT_CACHE.REFERENCE

Core-originated cacheable demand requests that refer to LLC

LSD.CYCLES_4_UOPS

Cycles 4 Uops delivered by the LSD, but didn't come from the decoder

LSD.CYCLES_ACTIVE

Cycles Uops delivered by the LSD, but didn't come from the decoder

LSD.UOPS

Number of Uops delivered by the LSD.

MACHINE_CLEARS.COUNT

Number of machine clears (nukes) of any type.

MACHINE_CLEARS.MASKMOV

This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.

MACHINE_CLEARS.MEMORY_ORDERING

Counts the number of machine clears due to memory order conflicts.

MACHINE_CLEARS.SMC

Self-modifying code (SMC) detected.

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT

Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM

Retired load uops which data sources were HitM responses from shared LLC.

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS

Retired load uops which data sources were HitM responses from shared LLC.

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS

Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS

Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS

Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE

Retired load uops which data sources were hits in LLC without snoops required.

MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE_PS

Retired load uops which data sources were hits in LLC without snoops required.

MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM

Retired load uops which data sources missed LLC but serviced from local dram.

MEM_LOAD_UOPS_RETIRED.HIT_LFB

Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.

MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS

Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.

MEM_LOAD_UOPS_RETIRED.L1_HIT

Retired load uops with L1 cache hits as data sources.

MEM_LOAD_UOPS_RETIRED.L1_HIT_PS

Retired load uops with L1 cache hits as data sources.

MEM_LOAD_UOPS_RETIRED.L1_MISS

Retired load uops which data sources following L1 data-cache miss

MEM_LOAD_UOPS_RETIRED.L1_MISS_PS

Retired load uops which data sources following L1 data-cache miss.

MEM_LOAD_UOPS_RETIRED.L2_HIT

Retired load uops with L2 cache hits as data sources.

MEM_LOAD_UOPS_RETIRED.L2_HIT_PS

Retired load uops with L2 cache hits as data sources.

MEM_LOAD_UOPS_RETIRED.L2_MISS

Miss in mid-level (L2) cache. Excludes Unknown data-source.

MEM_LOAD_UOPS_RETIRED.L2_MISS_PS

Retired load uops with L2 cache misses as data sources.

MEM_LOAD_UOPS_RETIRED.LLC_HIT

Retired load uops which data sources were data hits in LLC without snoops required.

MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS

Retired load uops which data sources were data hits in LLC without snoops required.

MEM_LOAD_UOPS_RETIRED.LLC_MISS

Miss in last-level (L3) cache. Excludes Unknown data-source.

MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS

Miss in last-level (L3) cache. Excludes Unknown data-source.

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128

Loads with latency value being above 128

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16

Loads with latency value being above 16

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256

Loads with latency value being above 256

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32

Loads with latency value being above 32

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4

Loads with latency value being above 4

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512

Loads with latency value being above 512

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64

Loads with latency value being above 64

MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8

Loads with latency value being above 8

MEM_TRANS_RETIRED.PRECISE_STORE

Sample stores and collect precise store operation via PEBS record. PMC3 only.

MEM_UOPS_RETIRED.ALL_LOADS

Load uops retired to architected path with filter on bits 0 and 1 applied.

MEM_UOPS_RETIRED.ALL_LOADS_PS

Load uops retired to architected path with filter on bits 0 and 1 applied.

MEM_UOPS_RETIRED.ALL_STORES

Store uops retired to architected path with filter on bits 0 and 1 applied.

MEM_UOPS_RETIRED.ALL_STORES_PS

Store uops retired to architected path with filter on bits 0 and 1 applied.

MEM_UOPS_RETIRED.LOCK_LOADS

Load uops with locked access retired to architected path.

MEM_UOPS_RETIRED.LOCK_LOADS_PS

Load uops with locked access retired to architected path.

MEM_UOPS_RETIRED.SPLIT_LOADS

Line-splitted load uops retired to architected path.

MEM_UOPS_RETIRED.SPLIT_LOADS_PS

Line-splitted load uops retired to architected path.

MEM_UOPS_RETIRED.SPLIT_STORES

Line-splitted store uops retired to architected path.

MEM_UOPS_RETIRED.SPLIT_STORES_PS

Line-splitted store uops retired to architected path.

MEM_UOPS_RETIRED.STLB_MISS_LOADS

Load uops with true STLB miss retired to architected path.

MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS

Load uops with true STLB miss retired to architected path.

MEM_UOPS_RETIRED.STLB_MISS_STORES

Store uops with true STLB miss retired to architected path.

MEM_UOPS_RETIRED.STLB_MISS_STORES_PS

Store uops true STLB miss retired to architected path.

MISALIGN_MEM_REF.LOADS

Speculative cache line split load uops dispatched to L1 cache

MISALIGN_MEM_REF.STORES

Speculative cache line split STA uops dispatched to L1 cache

MOVE_ELIMINATION.INT_ELIMINATED

Number of integer Move Elimination candidate uops that were eliminated.

MOVE_ELIMINATION.INT_NOT_ELIMINATED

Number of integer Move Elimination candidate uops that were not eliminated.

MOVE_ELIMINATION.SIMD_ELIMINATED

Number of SIMD Move Elimination candidate uops that were eliminated.

MOVE_ELIMINATION.SIMD_NOT_ELIMINATED

Number of SIMD Move Elimination candidate uops that were not eliminated.

OFFCORE_REQUESTS.ALL_DATA_RD

Demand and prefetch data reads

OFFCORE_REQUESTS.DEMAND_CODE_RD

Cacheable and noncachaeble code read requests

OFFCORE_REQUESTS.DEMAND_DATA_RD

Demand Data Read requests sent to uncore

OFFCORE_REQUESTS.DEMAND_RFO

Demand RFO requests including regular RFOs, locks, ItoM

OFFCORE_REQUESTS_BUFFER.SQ_FULL

Cases when offcore requests buffer cannot take more entries for core

OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD

Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD

Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD

Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD

Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore

OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO

Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD

Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD

Offcore outstanding Demand Data Read transactions in uncore queue.

OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO

Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore

OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE_0

Counts all demand & prefetch code reads that hit in the LLC

OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE_1

Counts all demand & prefetch code reads that hit in the LLC

OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0

Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1

Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM_0

Counts all demand & prefetch code reads that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM_1

Counts all demand & prefetch code reads that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE_0

Counts all demand & prefetch data reads

OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE_1

Counts all demand & prefetch data reads

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE_0

Counts all demand & prefetch data reads that hit in the LLC

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE_1

Counts all demand & prefetch data reads that hit in the LLC

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0

Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1

Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0

Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1

Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0

Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1

Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM_0

Counts all demand & prefetch data reads that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM_1

Counts all demand & prefetch data reads that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE_0

Counts all prefetch RFOs that hit in the LLC

OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED_0

Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE_0

Counts all data/code/rfo references (demand & prefetch)

OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE_1

Counts all data/code/rfo references (demand & prefetch)

OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE_1

Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC

OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED_1

Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM_0

Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM_1

Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCE.ANY_RESPONSE_0

Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC

OFFCORE_RESPONSE.ALL_READS.LLC_REFERENCE_ANY.ANY_RESPONSE_1

Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC

OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE_0

Counts all demand & prefetch prefetch RFOs

OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE_1

Counts all demand & prefetch prefetch RFOs

OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE_0

Counts all demand & prefetch RFOs that hit in the LLC

OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE_1

Counts all demand & prefetch RFOs that hit in the LLC

OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED_0

Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED_1

Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_0

Counts all writebacks from the core to the LLC

OFFCORE_RESPONSE.COREWB.ANY_RESPONSE_1

Counts all writebacks from the core to the LLC

OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM_0

Counts LLC replacements

OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM_1

Counts LLC replacements

OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE_0

Counts all demand code reads

OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE_1

Counts all demand code reads

OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_0

Counts all demand code reads that hit in the LLC

OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE_1

Counts all demand code reads that hit in the LLC

OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_0

Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED_1

Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM_0

Counts demand code reads that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM_1

Counts demand code reads that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE_0

Counts all demand data reads

OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE_1

Counts all demand data reads

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_0

Counts all demand data reads that hit in the LLC

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE_1

Counts all demand data reads that hit in the LLC

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_0

Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE_1

Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_0

Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD_1

Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_0

Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED_1

Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM_0

Counts demand data reads that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM_1

Counts demand data reads that miss the LLC and the data returned from dram

OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE_0

Counts all demand rfo's

OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE_1

Counts all demand rfo's

OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE_0

Counts all demand data writes (RFOs) that hit in the LLC

OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE_1

Counts all demand data writes (RFOs) that hit in the LLC

OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_0

Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE_1

Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded

OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED_0

Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED_1

Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores

OFFCORE_RESPONSE.OTHER.ANY_RESPONSE_0

Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches

OFFCORE_RESPONSE.OTHER.ANY_RESPONSE_1

Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches

OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC_1

Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses

OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_0

Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address

OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE_1

Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address

OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_0

Counts non-temporal stores

OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE_1

Counts non-temporal stores

OTHER_ASSISTS.ANY_WB_ASSIST

Number of times any microcode assist is invoked by HW upon uop writeback.

OTHER_ASSISTS.AVX_STORE

Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.

OTHER_ASSISTS.AVX_TO_SSE

Number of transitions from AVX-256 to legacy SSE when penalty applicable.

OTHER_ASSISTS.SSE_TO_AVX

Number of transitions from SSE to AVX-256 when penalty applicable.

PAGE_WALKS.LLC_MISS

Number of any page walk that had a miss in LLC.

RESOURCE_STALLS.ANY

Resource-related stall cycles

RESOURCE_STALLS.ROB

Cycles stalled due to re-order buffer full.

RESOURCE_STALLS.RS

Cycles stalled due to no eligible RS entry available.

RESOURCE_STALLS.SB

Cycles stalled due to no store buffers available. (not including draining form sync).

ROB_MISC_EVENTS.LBR_INSERTS

Count cases of saving new LBR

RS_EVENTS.EMPTY_CYCLES

Cycles when Reservation Station (RS) is empty for the thread

RS_EVENTS.EMPTY_END

Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.

SIMD_FP_256.PACKED_DOUBLE

number of AVX-256 Computational FP double precision uops issued this cycle

SIMD_FP_256.PACKED_SINGLE

number of GSSE-256 Computational FP single precision uops issued this cycle

TLB_FLUSH.DTLB_THREAD

DTLB flush attempts of the thread-specific entries

TLB_FLUSH.STLB_ANY

STLB flush attempts

UNC_ARB_COH_TRK_OCCUPANCY.ALL

Cycles weighted by number of requests pending in Coherency Tracker.

UNC_ARB_COH_TRK_REQUESTS.ALL

Number of requests allocated in Coherency Tracker.

UNC_ARB_TRK_OCCUPANCY.ALL

Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.

UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL

Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.

UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST

Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.

UNC_ARB_TRK_REQUESTS.ALL

Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.

UNC_ARB_TRK_REQUESTS.EVICTIONS

Counts the number of LLC evictions allocated.

UNC_ARB_TRK_REQUESTS.WRITES

Counts the number of allocated write entries, include full, partial, and LLC evictions.

UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER

Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.

UNC_CBO_CACHE_LOOKUP.E

LLC lookup request that access cache and found line in E-state.

UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER

Filter on external snoop requests.

UNC_CBO_CACHE_LOOKUP.I

LLC lookup request that access cache and found line in I-state.

UNC_CBO_CACHE_LOOKUP.M

LLC lookup request that access cache and found line in M-state.

UNC_CBO_CACHE_LOOKUP.READ_FILTER

Filter on processor core initiated cacheable read requests.

UNC_CBO_CACHE_LOOKUP.S

LLC lookup request that access cache and found line in S-state.

UNC_CBO_CACHE_LOOKUP.WRITE_FILTER

Filter on processor core initiated cacheable write requests.

UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER

Filter on cross-core snoops initiated by this Cbox due to LLC eviction.

UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER

Filter on cross-core snoops initiated by this Cbox due to external snoop request.

UNC_CBO_XSNP_RESPONSE.HIT

A snoop hits a non-modified line in some processor core

UNC_CBO_XSNP_RESPONSE.HITM

A snoop hits a modified line in some processor core.

UNC_CBO_XSNP_RESPONSE.INVAL

A snoop invalidates a non-modified line in some processor core

UNC_CBO_XSNP_RESPONSE.INVAL_M

A snoop invalidates a modified line in some processor core

UNC_CBO_XSNP_RESPONSE.MISS

A snoop misses in some processor core.

UNC_CBO_XSNP_RESPONSE.XCORE_FILTER

Filter on cross-core snoops initiated by this Cbox due to processor core memory request.

UNC_CLOCK.SOCKET

This 48-bit fixed counter counts the UCLK cycles

UOPS_DISPATCHED_PORT.PORT_0

Cycles per thread when uops are dispatched to port 0

UOPS_DISPATCHED_PORT.PORT_0_CORE

Cycles per core when uops are dispatched to port 0

UOPS_DISPATCHED_PORT.PORT_1

Cycles per thread when uops are dispatched to port 1

UOPS_DISPATCHED_PORT.PORT_1_CORE

Cycles per core when uops are dispatched to port 1

UOPS_DISPATCHED_PORT.PORT_2

Cycles per thread when load or STA uops are dispatched to port 2

UOPS_DISPATCHED_PORT.PORT_2_CORE

Uops dispatched to port 2, loads and stores per core (speculative and retired)

UOPS_DISPATCHED_PORT.PORT_3

Cycles per thread when load or STA uops are dispatched to port 3

UOPS_DISPATCHED_PORT.PORT_3_CORE

Cycles per core when load or STA uops are dispatched to port 3

UOPS_DISPATCHED_PORT.PORT_4

Cycles per thread when uops are dispatched to port 4

UOPS_DISPATCHED_PORT.PORT_4_CORE

Cycles per core when uops are dispatched to port 4

UOPS_DISPATCHED_PORT.PORT_5

Cycles per thread when uops are dispatched to port 5

UOPS_DISPATCHED_PORT.PORT_5_CORE

Cycles per core when uops are dispatched to port 5

UOPS_EXECUTED.CORE

Number of uops executed on the core.

UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC

Cycles where at least 1 uop was executed per-thread

UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC

Cycles where at least 2 uops were executed per-thread

UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC

Cycles where at least 3 uops were executed per-thread

UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC

Cycles where at least 4 uops were executed per-thread

UOPS_EXECUTED.STALL_CYCLES

Counts number of cycles no uops were dispatched to be executed on this thread.

UOPS_EXECUTED.THREAD

Counts the number of uops to be executed per-thread each cycle.

UOPS_ISSUED.ANY

Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)

UOPS_ISSUED.CORE_STALL_CYCLES

Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads

UOPS_ISSUED.FLAGS_MERGE

Number of flags-merge uops being allocated.

UOPS_ISSUED.SINGLE_MUL

Number of Multiply packed/scalar single precision uops allocated

UOPS_ISSUED.SLOW_LEA

Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.

UOPS_ISSUED.STALL_CYCLES

Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread

UOPS_RETIRED.ALL

Actually retired uops.

UOPS_RETIRED.ALL_PS

Retired uops.

UOPS_RETIRED.CORE_STALL_CYCLES

Cycles without actually retired uops.

UOPS_RETIRED.RETIRE_SLOTS

Retirement slots used.

UOPS_RETIRED.RETIRE_SLOTS_PS

Retirement slots used.

UOPS_RETIRED.STALL_CYCLES

Cycles without actually retired uops.

UOPS_RETIRED.TOTAL_CYCLES

Cycles with less than 10 actually retired uops.